Homebrew FPGAs

Homebrew CPUs made out of logic chips are nothing new, but a homebrew FPGA is another matter entirely. [Joshua] sent in a project he whipped up where he made a single logic cell FPGA.

Despite how complicated and intimidating they are in practice, FPGAs are really very simple. They’re made of thousands of logic blocks capable of transmuting into AND, OR, NAND, and XOR logic gates. These logic blocks are all tied together, and with a somewhat complex hardware design language are capable of becoming a CPU, a micocontroller, or even a video card. Basically, programming a microcontroller tells a chip what to do, while programming an FPGA tells the chip what to be.

To build his single logic block FPGA, [Joshua] used a four-bit multiplexer to hard wire a truth table out of a 74HC174 D-type flip-flop. A bit of Arduino code changes the state of the pins connected to the multiplexer allows for any combination of TRUE and FALSE to be calculated for AND, NAND or XOR logic functions.

Yes, it’s only a single logic block for an FPGA, and if this build were expanded to even a few hundred cells it would be gargantuan. Still, there’s no better way to learn the ins and outs of abstract hardware, so we’ll gladly tip our hat to [Joshua] and his homebrew FPGA.

Comments

  1. crenn says:

    That’s actually pretty good and would be a good insight for a begineer to how FPGAs work

  2. regulatre says:

    Nice work! In terms of ADC Bits and bit rate (thinking in terms of SDR) what is the sample rate and number of bits per sample?

  3. DanJ says:

    I think this is neat and kudos to Joshua. But the HaD editor’s statement “Still, there’s no better way to learn the ins and outs of abstract hardware,” made my wince and laugh at the same time. I hope the implication of that isn’t that FPGAs are the beginning and end of digital design. One might google Karnaugh maps, combinatorial logic design, finite state machines, etc, etc for that.

  4. ninoscript says:

    Next step, port the design to HDL, and burn it into an FPGA!
    Oh… wait.

  5. salec says:

    Use a SIPO shift register (e.g. 74HC595) instead of 74HC174 and then you can even program your FPGA using JTAG (SPI), like real stuff.

  6. guan says:

    ninoscript: I’ve long wondered if anyone has ever created an FPGA on an FPGA. The benefit would be that you fully understand the bitstream and don’t need to rely on proprietary tools to program your (top) FPGA.

    • Spork says:

      Yes, but then you need an FPGA big enough to fit the FPGA, which in turn has to be large enough to fit your own design. More than likely the physical FPGA would need to be several times larger than the one you would need to just implement your own design by itself.

      Plus, there’s the issue of having to develop your own toolchain. Not exactly trivial.

      I’m all for open-source, but FPGA’s are relatively expensive devices. There’s no getting around it.

    • robbie says:

      That is an awesome idea!
      Any propgation delay should be small (-ish, and deterministic), and getting rid of the horrible vendor software for something custom/open would be well worth the loss in capacity (program from OS X? yes please!).
      Also, developing a custom toolchain would be the most fun part of the project. No, not trivial, but not exactly something you’d have to spend a lot of time talking somebody into doing.

    • FPGA_dude says:

      Yeah, “virtual FPGAs” are actually a real thing. Do a google search for “intermediate fabrics”.

    • Mike Field says:

      Possible to make virtual programmable logic cell – Check!

      Possible to make programmable connections between virtual cells – umm…

    • Mike Field says:

      Nice work!

      It is a 2 input LUT, so a 4 input LUT would take about four breadboards, and as a Spartan 3 logic slice has 2 of these, making it equivalent to about 8 breadboards of logic…

      Wow! A Spartan 3E -500 is equipment to around 3,500 breadboards.

      • gyro john says:

        … is to …

        drat you, autoCucumber!

      • Sheldon says:

        Actually, it depends upon how the LUT is designed. Think of this example (2-inputs, 1-output) as a 1-bit memory that has a 2-bit address. To do a 4-input LUT then you’d be needing a memory chip that has 4 address lanes. This is in fact how a lot of LUT actually work internally (they also have extra logic for storage of state and other stuff that is skipped over in this example).

  7. Mikey says:

    By definition doesn’t an FPGA have to have more than one logic block? It’s like how saying you have a RAID array with just one drive doesn’t make any sense.

    Seems to me this is a PG — “Programmable Gate” — it’s not really field programmable, since you wouldn’t deploy a breadboard to the field — and it’s not an array since there’s only one programmable gate. And actually it looks like there’s no way to load the program from ROM and latch it …. so maybe it’s more of a “Configurable” gate, since in practice you would need a jumper or some kind of constant config data being pumped in externally (say from an Arduino) to make it work.

    • Hamster says:

      Nobody says you have to instantiate *all* your logic blocks at once… I’m sure he has enough bits for a second one in a draw somewhere…

      :-)

      • Mikey says:

        That’s the other thing, I was thinking about this some more — and even if it was an array, it’s still missing the reprogrammable interconnects — Even if he adds more — it becomes a monster GAL (Gate Array Logic) rather than FPGA…

        What I’d like to see is someone do a homebrew FPGA from an array of interconnected GAL chips. Maybe I’ll have to do that sometime…

  8. dbear says:

    I always said you could build anything with enough TTL chips. And enough space. And enough power. And enough cooling.

  9. rewolff says:

    As a “chip desgin excercise” I desgined a, what later would be called, FPGA back around 1988 or so. The teacher thought it was useless. It had more than one, but not very many cells. I remember a number like 256, but that might have been the total number of configuration bits….. I used WAY too many transistors for each configuration D-flipflop, so that’s all that would fit with the 1.6 micron process that we were supposed to design with….

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