TMS9900 Retro Build

[Robert Baruch] found a TMS9900 CPU from 1983 in a surplus store. If that name doesn’t ring a bell, the TMS9900 was an early 16-bit CPU from Texas Instruments. He found that, unlike modern CPUs, the chip took several voltages and a four-phase twelve-volt clock. He decided to fire it up and — of course — one thing led to another and he wound up with a system on a breadboard. You can see one of the videos he made about the machine below.

This CPU had some odd features, most notably that it stored its registers in off-chip memory and can switch contexts by changing where the registers reside. That was a novel idea when the memory and the CPU were similar in speed. In a modern computer, the memory is much slower than the CPU and this would be a major bottleneck for program execution. The only onboard registers were the program counter, the status register, and a pointer to the general-purpose registers in memory.

[Robert] doesn’t quite have a full system yet, but we bet he’ll get there. He built a four-digit display and did some simple control line decoding of the processor. He can watch the address bus and also manages to single step. The TMS9900 used dynamic logic, so you can’t just halt the clock. However, there is a way to do it with a state machine [Robert] built with some flip flops and an ATmega processor.

To overcome the fast memory problem, TI’s TI-99/4 home computer only had 128 words of memory directly addressable. Main program storage was cheaper and slower dynamic RAM (16 K bytes) that you could only access via the display controller. This meant performance suffered. If you had the optional floppy controller, you got extra RAM, but that was pricey in the day.

We recently saw a TI 99/4A doing service as a weather station. If [Robert] duplicates the TI-99/4 display system, maybe he can run this demo. We are waiting to see where [Robert] takes his surplus store find from here.

22 thoughts on “TMS9900 Retro Build

  1. DRAM was fast enough for the TMS9900, but for the CPU to run at full speed it needed to be 16 bits wide. TI marketing didn’t want the 99/4A to impact on their mini computer sales, so they deliberately hamstrung it by using 8 bit wide memory for all but the 256 byte scratchpad RAM.

    1. “DRAM was fast enough for the TMS9900”

      Not in the early 80s it wasn’t.

      Hardware designers, such as myself, had a stark choice then. Fast or Cheap (ish).

      For the ‘home’ and ‘small business’ markets, the choice was pretty obvious as neither market would bear the cost of Fast. Hence the ‘cut-down’ versions of the 68000 and 8086 among others. Smaller data and address buses, smaller packaging, lower pin count, lower cost.

      Semiconductor memory had a similar issue. Static ram was faster but had a lower per-chip capacity and cost more than DRAM. To achieve the same ‘total’ capacity using static ram required more chips, more board space and cost a lot more.

      1. Nonsense. The 4116 DRAM chip dates back to 1977 and, even in its slowest incarnation, could manage a read or write in about 400ns.
        Manufacturers tried to save money by building smaller boards with fewer chips, which is why they liked to use 8 rather than 16 bit chip, but at the price point the 99/4a was aimed at they could have quite easily managed 16 rather than 8 16 pin RAM chips. They had already covered the major expensed of the TMS9900 CPU and the attendant circuitry it needed (3 power rails, a 4 phase clock generator etc). This wasn’t meant to be a cheap machine.

        1. Yes. Let’s all blame the manufacturers. After all, if it wasn’t for those greedy bastards insisting on being paid for their work we could all have what we wanted for free.

        2. A bit contradictory there…

          First you claim it’s because the manufacturers wanted to save money, then you claim they could easily managed “16 rather than 8 16 pin RAM chips”.

          The latter simple isn’t true of course. Doubling the number of DRAM chips would have meant more board space at a time when multilayer boards cost ‘an arm and a leg’. Add in more control logic, more complex layout, bigger case, etc. and the end result is higher costs all round.

          I used to do this for a living and one of our primary motivating concerns at the time was production costs which were much higher then.

          1. You missed the bit about the 99/4A not being targeted as a cheap machine. They had already committed to a TMS9900 (in a 64 pin package no less), plus all the support hardware to make it work. It was launched at about the same time as the BBC Model B and Spectrum, for more money and with less RAM (the Spectrum used 4116s for the lower 16K of its memory map. 16 DRAM chips on a motherboard was pretty standard fair, and 4116s were far from the ultimate in performance – the 4816 in the BBC B for example was quick enough to serve both its 2MHz 6502 and the video subsystem at the same time, with a 250ns cycle time). The TMS9900 had a fairly relaxed memory cycle of just under 2 clocks, which given it ran at 3MHz put its needs at about 580ns.

          2. Sweeney, I did not miss the bit about the TI-99/4(A) target price point.

            You however, seem to have missed the point about manufacturing costs.

            Your primary argument seems to be ‘they did it, why can’t you’, which is like comparing chalk and cheese on the basis of flavour, and concluding that cheese is better because it tastes better.

            Your arguments about dram speed are more of the same. Different machines. different architectures, different design choices. In a memory to memory architecture such as the TMS9900, memory access speed is crucial and at that point in time, DRAM was the slow option. i.e. it wasn’t fast enough for the TMS9900.

            More importantly, I did not say they couldn’t do it. I tried to explain some of what may have been driving their choices. e.g. manufacturing costs.

            Finally, as Robert alluded to above, it simply wasn’t selling at it’s original price point and was repeatedly discounted (eventually to around $150 without monitor) in an effort to drive sales.

  2. That’s great. The first task switcher I ever worked with used that feature for context switching. Save three registers, update same and you’re off. Semaphores, bah!! :-)

  3. This CPU was used in the Weigh-Tronix WI-110 industrial scale display, which was manufactured from 1981 through some point in the 1990’s when TI stopped making the chips. At some point they switched from the 9900 to the 9995, but al the peripherals remained compatible. That unit also used the TMS9901 peripheral interface which generates the complicated clock needed by the 9900 and also provides a bunch of individually addressible I/O pins and a counter-timer which was integral to the WI-110’s analog to digital converter.

  4. “This CPU had some odd features, most notably that it stored its registers in off-chip memory”

    This is only ‘odd’ by post Intel/Microsoft standards. There were a number of mid to high end minicomputers which had this architectural feature or something similar, most notably the TI-990 series. The TMS9900 was a single chip version of the TI-990 CPU.

    1. That does have the added benefit of being able to cycle through banks of register memory using hardware, thus producing a real time multi-user environment by changing the register memory and changing the base user memory window at the same time. True multi-user/multi process ability with shared peripherals like a main hard drive and printer among all the users. See CADO Systems CAT III, CONTEL CADO SYSTEM IV, or CONTEL TIGER – a multi-user terminal system (3 to 64 users) for much less than a DEC or IBM system – IN THE late 70’s-early to mid 80’s, they used similar window switching magic on a 8085, and later a 68000 – programmed in CADOL II and CADOL III. Yes, another dead sea language….

      1. I suspect that fast context switching was one of the primary design criteria. Save/reload three registers and you’re good to go. It would have had a significant impact on multi-user/multitasking and I/O performance.

          1. It was indeed a trade off at the time. For a mid to high end mini, you would use high speed static ram throughout. For ‘lower’ cost machines you would use a small ‘scratchpad’ area of high speed static ram and the rest would be slower DRAM. This is design the TI-99/4(A) used.

            Now, memory to memory architecture simply isn’t viable in a general purpose cpu.

  5. This reminds me, I have a recently acquired Texas Instruments DS990 Model 1 system sitting in my lounge at home that I still need to power on and try to get working…

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