Gravity can be a difficult thing to simulate effectively on a traditional CPU. The amount of calculation required increases exponentially with the number of particles in the simulation. This is an application perfect for parallel processing.
For their final project in ECE5760 at Cornell, [Mark Eiding] and [Brian Curless] decided to use an FPGA to rapidly process gravitational calculations. This allows them to simulate a thousand particles at up to 10 frames per second. With every particle having an attraction to every other, this works out to an astonishing 1 million inverse-square calculations per frame!
The team used an Altera DE2-115 development board to build the project. General operation is run by a Nios II processor, which handles the VGA display, loads initial conditions and controls memory. The FPGA is used as an accelerator for the gravity calculations, and lends the additional benefit of requiring less memory access operations as it runs all operations in parallel.
This project is a great example of how FPGAs can be used to create serious processing muscle for massively parallel tasks. Check out this great article on sorting with FPGAs that delves deeper into the subject. Video after the break.
Continue reading “Gravity Simulations With An FPGA”
Hackaday reader [nats.fr] wrote in with some code from a project that resizes a video stream on the fly using an FPGA. Doing this right means undoing whatever gamma correction has been applied to the original stream, resizing, and then re-applying the gamma. Making life simpler, [nats.fr] settled on a gamma of two, which means taking a bunch of square roots, which isn’t fast on an FPGA.
[nats]’s algorithm is pretty neat: it uses a first-stage lookup to figure out in which broad range the value lies, and then one step of Hero’s algorithm to refine from there. (We think this is equivalent to saying he does a piecewise linear interpolation, but we’re not 100% sure.) Anyway, it works decently.
Of course, when you start looking into the abyss that is special function calculation, you risk falling in. Wikipedia lists more methods of calculating square roots than we have fingers. One of them, CORDIC, avoids even using multiplication by resorting to clever bitshifts and a lookup table. Our go-to in these type of situations, Chebyshev polynomial approximation, didn’t even make the cut. (Although we suspect it would be a contender in the
gamma=2.2 cases, especially if combined with range-reduction in a first stage like [nats.fr] does.)
So what’s the best/fastest approximation for
sqrt(x) for 16-bit integers on an FPGA? [nats.fr] is using a Spartan 6, so you can use a multiplier, but division is probably best avoided. What about arbitrary, possibly fractional, roots?
On my way to this year’s Hackaday SuperConference I saw an article on EE Times about someone taking the $22 Lattice iCEstick and turning it into a logic analyzer complete with a Python app to display the waveforms. This jumped out as pretty cool to me given that there really isn’t a ton of RAM on the stick, basically none that isn’t contained in the FPGA itself.
[Jenny List] has also written about the this application as created by [Kevin Hubbard] of Black Mesa Labs and [Al Williams] has a great set of posts about using this same $22 evaluation board doing ground up Verilog design using open source tools. Even if you don’t end up using the stick as a logic analyzer over the long haul, it’ll be very easy to find many other projects where you can recompile to invent a new purpose for it.
Continue reading “Compiling a $22 Logic Analyzer”
Here’s a business plan for you, should you ever run into an old silicon fab sitting in a dumpster: build Commodore SID chips. The MOS 6581 and 8580 are synthesizers on a chip, famously used in the demoscene, and even today command prices of up to $40 USD per chip. There’s a market for this, and with the right process, this could conceivably be a viable business plan.
Finding a silicon fab in a dumpster is a longshot, but here’s the next best thing: an FPGASID project. The FPGASID is a project to re-create the now-unobtanium MOS 6581 found in the Commodore 64.
The Commodore SID chip has been out of production for a while now, and nearly every available SID chip has already been snapped up by people building MIDIbox SIDs, or by Elektron for their SidStation, which has been out of production for nearly a decade. There is a demand for SID chips, one that has been filled by “clones” or recreations using ATmegas, Propellers, and nearly every other microcontroller architecture available. While these clones can get the four voices of the SID right, there’s one universal problem: the SID had analog filters, and no two SIDs ever sounded alike.
From the audio samples available on the project page for the FPGASID, the filters might be a solved problem. The output from the FPGASID sounds a lot like the output from a vintage SID. Whether or not this is what everyone agrees a SID should sound like is another matter entirely, but this is the best attempt so far to drag the synth on a chip found in the Commodore 64 into modern times.
The files, firmware, and FPGA special sauce aren’t available yet, but the FPGASID is in alpha testing, with a proper release tentatively scheduled for early 2017. Maybe now it’s time to dig out those plans for the Uber MIDIbox, with octophonic SID goodness.
FPGAs are the future, and there’s a chip out there that brings us the future today. I speak, of course, of the Xilinx Zynq, a combination of a high-power ARM A9 processor and a very capable FPGA. Now the Zynq has been made Pynq with a new dev board from Digilent.
The heart of this board, is, of course, the Xilinx Zynq packing a Dual-core ARM Cortex A9 processor and an FPGA with 1.3 Million reconfigurable gates. This is a dev board, though, and with that comes memory and peripherals. To the board, Digilent added 512MB of DDR3 RAM, a microSD slot, HDMI in and out, Ethernet, USB host, and GPIOs, some of which match the standard Arduino configuration.
This isn’t the first Zynq board out there by any measure. Last year, [antti] had a lot of fun with the Zynq and created the ZynqBerry, a Zynq in a Raspberry Pi form factor, and a Zynq Arduino shield. Barring that, we’ve seen the Zynq in a few research projects, but not so much in a basic dev board. The Pynq Zynq is among the first that will be produced in massive quantities.
There is, of course, one downside to the Pynq Zynq, and that is the price. It’s $229 USD, or $65 with an educational discount. That’s actually not that bad for what you’re getting. FPGAs will always be more expensive than an SoC stolen from a router or cell phone, no matter how powerful it is. That said, putting a powerful ARM processor and a hefty FPGA in a single package is an interesting proposition. Adding HDMI in and out even more so. Already we’ve seen a few interesting applications of the Zynq like synthesizers, quadcopters, and all of British radio. With this new board, hopefully a few enterprising FPGA gurus will pick one up and tell the rest of us mere mortals how to do some really cool stuff.
In part one, I compared the different Analog to Digital Converters (ADC) and the roles and properties of Delta Sigma ADC’s. I covered a lot of the theory behind these devices, so in this installment, I set out to find a design or two that would help me demonstrate the important points like oversampling, noise shaping and the relationship between the signal-to-noise ratio and resolution.
Check out part one to see the block diagrams of what what got us to here. The schematics shown below are of a couple of implementations that I played with depicting a single-order and a dual-order Delta Sigma modulators.
Basically I used a clock enabled, high speed comparator, with two polarities in case I got it the logic backwards in my current state of burn out to grey matter ratio. The video includes the actual schematic used.
Since I wasn’t designing for production I accepted the need for three voltages since my bench supply was capable of providing them and this widget is destined for the drawer with the other widgets made for just a few minutes of video time anyway. Continue reading “Tearing into Delta Sigma ADCs Part 2”
A few years ago, [Kingpin] a.k.a. [Joe Grand] (A judge for the 2014 Hackaday Prize) designed the most beautiful electronic prank ever. The BSODomizer is a simple device with a pass-through connection for a VGA display and an infrared receiver. Plug the BSODomizer into an unsuspecting coworker’s monitor, press a button on a remote, and watch Microsoft’s blue screen of death appear. It’s brilliant, devious, and actually a pretty simple device if you pick the right microcontroller.
The original BSODomizer is getting a little long in the tooth. VGA is finally dead. The Propeller chip used to generate the video only generates text, and can’t reproduce Microsoft’s fancy new graphical error screens. HDMI is the future, and FPGAs have never been more accessible. For this year’s DEF CON, [Kingpin] and [Zoz] needed something to impress an audience that is just learning how to solder. They’ve revisited the BSODomizer, and have created the greatest hardware project at this year’s DEF CON.
Continue reading “DEF CON: BSODomizing In High Definition”