Design Your Own Processor With Verilog

Intel-sandy

Designing a computer from scratch is one of the holy grails of hardware design. For programmable logic, designing your own processor is a huge accomplishment. That’s exactly what [zhemao] has done. He created EZ8, an 8 bit processor is written in Verilog. EZ8 has a 3 stage pipeline, which makes design very interesting. Instruction set pipelines have been used in processors for many years. They speed up operation by allowing the processor to execute more than one instruction in parallel. The idea is similar to washing, drying and folding laundry. Most people pipeline their laundry. One load is in the washer, another in the dryer, and a third is being folded. Pipelines aren’t a free lunch though – there are hazards. If one instruction requires the result of an instruction which is still being executed in parallel, there’s a problem. In our laundry analogy this would be like having one sock on the folding table while its mate is still in the dryer. The folding operation must wait for the drying operation to complete before the socks can be paired. This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.

[zhemao] didn’t just give us a processor and no support though. He also included an assembler written in OCaml, and an emulator written in C. Several test assembly programs are also up on [zhemao’s] github repo  to verify operation. [zhemao] has tested his processor with Altera Cyclone 5 series FPGAs, but it should be possible to port it to other FPGA manufacturers. If you want more information, [zhemao] also has a discussion going on in the ECE subreddit.

[Thanks for the tip LongHornEngineer!]

[Image courtesy of intel]

Introducing the FleaFPGA Experimenter’s Board

[Valentin] recently tipped us about an FPGA development board he just finished. It is called the FleaFPGA and is aimed to get people interested in the world of Field Programmable Gate Arrays. One of the other reasons that also got [Valentin] to design his own board was that he was frustrated with the existing solutions, them being either too pricey or fairly spare in terms of connectivity.

The main components that you can see in the platform shown above are: a lattice MachX02-7000HE FPGA (6864LUTs), 256Mbits of SDRAM, a USB2.0 host port, a 4096-color VGA connector, a 3.5mm stereo connector, an SD/MMC card slot, a PS/2 keyboard/mouse combo port, a few push buttons and LEDs. An expansion header is also present in order to connect the FleaFPGA to future shields that will be developed. Unfortunately only the board schematics have been released and [Valentin] is currently aiming for a price of $60 per board for <100 quantities. You’ll be able to see a video of the board in action after the break, in which the FPGA has been loaded with a 68000 software core running a variation of the Amiga Juggler Demo.

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Designing Flip-Flops with Python and Migen

migen

Flip-flops are extremely simple electronic circuits, forming the basis of clock circuits, memory circuits, buffers, and shift registers. Through his dilly-dallying with digital logic, [Jeffrey] decided he would build his own. Not with Verilog or VHDL, though, but Migen: the Python-based way to build digital circuits with software.

Migen is an interesting tool that makes traditional FPGA programming a lot easier; instead of Verilog or VHDL, Migen allows an FPGA to be programmed in Python. Yes, it’s the tool you’ve been waiting for, and the tutorials make it look pretty easy. After installing Migen, [Jeff] wrote a class for a D flip-flop in only three lines of code. That’s three readable lines of code, and he was able to simulate the flip-flop with gtkwave in another two lines. Compared to learning the complexities of VHDL or Verilog, Migen makes digital logic and FPGA programming a breeze.

[Jeff] has a great tutorial for building a D flip-flop with Migen, but we’d love to see some more complex examples of what can be done with this very cool tool. If you’re building (or have built) something with Migen, be sure to send it in and relate your experiences.

A DiskVaccuum For Obsolete Disk Formats

drive

[Jim] has a box of disks for a very old Compucolor II computer, and with bit rot slowly setting in he figured it might be time to dump all those disks to a more permanent format. After reviewing the existing tools to read these disks, he decided to build his own floppy disk interface that he calls the DiskVaccuum.

The DiskVaccuum is based on a Papilio Pro FPGA board and a few chips worth of level conversion. The FPGA is able to read bits and move the head of the disk with ease, saving everything to the drive of a much more modern computer.

On the USB side of the Papilio board, [Jim] wrote a shell of sorts in Python to capture tracks on the disk, read out the track listing, save an image file, and do all the things a proper DOS should. Right now the project is only for the Compucolor II disk drive, but [Jim] played around with KiCAD enough to create a Papilio-to-disk-drive interface board with connectors for most of the disk drives of this particular vintage. The hope is to generalize the hardware and software to read disks for other systems, including those with 8-inch drives.

[Jim] put up a video describing the hardware and demoing his Python capture utility. You can check that out below.

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Fubarino Contest: FPGA Pong

pong

For [Eric]’s entry for our Fubarino Contest, he went down to very low-level hardware and created Pong on an FPGA.

[Eric] used a Basys 2 FPGA board to create this virtual, logic gate version of Pong. Output is via the VGA port, multiplayer and an AI player is implemented, and all the required mechanics for Pong – collision detection, button and switch input, and score keeping are also in this project.

The Fubarino contest requires an easter egg, of course, so when the score for the left player reaches 13 and the score for the right player reaches 37 (get it? 1337?), the previously square ball turns into an extremely pixeley version of the Hackaday logo. The Hackaday URL is also displayed, thanks to [Eric]’s FP(V)GA module for displaying text on his FPGA board.

The improved Pong ball and URL only appears when the scores are 13-37, making this an extremely well-hidden easter egg. Video of [Eric] demoing his Pong below.


This is an entry in the Fubarino Contest for a chance at one of the 20 Fubarino SD boards which Microchip has put up as prizes!

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Build an FPGA Microbee in Three (Not so) Easy Steps

Microbee,_Melbourne_Museum

[Brad Robinson] was feeling a bit nostalgic for his Microbee, so he rebuilt it in an FPGA. Not once, but three times. For the uninitiated, the Applied Technology Microbee was a Z80 based computer 1980’s. Designed in Australia, the Microbee did not see much popularity outside its home continent. Even so, the introduction to home computers many Australians was on a Microbee. [Brad] actually wrote several programs for the Microbee, including some games sold by Applied Technology themselves.

Fast forward to 2012, [Brad] is learning FPGAs, and wants to build a Microbee in VHDL. The FPGAbee was born. The first iteration of the FPGAbee began with the CPU, which came from the T80 open source VHDL Z80 core. Around this core [Brad] added the video controller, keyboard, and sound. When he started adding disk functionality, [Brad] ran into some problems. He wanted to use a FAT formatted SD card for cassette and hard disk emulation.

The relative complexities of the FAT format meant he would have to use some custom software to make this work. [Brad] decided to run this software on a second Z80 core. Both cores would need access to memory, and this is where [Brad] learned what he calls “a hard lesson in cross domain clocks” on FPGAs. Multiple clock nets can cause major propagation delay issues. [Brad] was able to work through the problems, but it caused him to step back and re-evaluate the entire design. This was the start of FPGABee2.

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SDRAM controller for low-end FPGAs

There are very few ‘recent’ FPGAs out there that can be easily soldered. Due to their important number of IOs, they usually come in Ball Grid Array (BGA) packages. The Xilinx Spartan 6 LX9, a TQFP144 FPGA (having pins with a 0.5mm pitch) is one of the few exceptions that can be used to make low end development boards. However, it doesn’t have a lot of logic and memory resources or an on-chip Memory Control Block implemented in the silicon. Therefore, [Michael] designed an SDRAM controller with a small footprint for it.

Writing an SDRAM controller from scratch isn’t for the fainthearted – first of all you really have to know how SDRAM  works (RAS, CAS, precharges, refresh cycles), and because of the high speed and accurate timing required you also have to learn some of the finer points of FPGA off-chip interfacing. In addition, most publicly available open cores are very complex – for example just the RTL core of the sdr_ctrl controller on opencores.org adds up to over 2,700 lines of Verilog. Even if it is not an accurate comparison metric, [Michael]’s controller is only 500 lines long.