It’s been a while since we’ve seen some new boards that combine an FPGA and an Arduino, so naturally the state of the art is a little bit behind. The latest from [Jack Gassett], the Papilio Duo, aims to change that by addressing all the complaints of the original Papilio and adding some neat, modern features that you would expect on a board designed in 2014.
On board the Duo is an ATMega32u4, the same chip used in the Arduino Leonardo, allowing for easy integration with your standard Arduino projects. The top of the board is where the real money is. There’s a Spartan 6 FPGA with 9k logic cells, enough to run emulate some of the classic computers of yore, including the famous SID chip, Yamaha YM2149, and the Atari POKEY (!). With host and device USB, 512k or 2M of SRAM, and an ADC on the FPGA inputs, this board should be able to handle just about everything you would want to throw at it. There’s even a breakout for HDMI on the bottom.
There are a few interesting software features of the Duo, including a full debugger for the ATMega chip, thanks to an emulated Atmel JTAG ICE MKII. Yes, an Arduino-compatible board finally has a real debugger. The FPGA can also implement a 32 channel logic analyzer, making this not only an extremely powerful dev board, but also a useful tool to keep around the workbench.
[Will] wrote a 128MHz Z80-based retro microcomputer which runs on a Papilio Pro board. For those who don’t know, the latter is built around a Spartan-6 LX9 FPGA so you may imagine that much work was required to implement all the computer features in VHDL. The T80 CPU core was taken from opencores, the SDRAM controller was imported from Mike Field’s work but [Will] implemented several additional functions on his own:
– a 4KB paged Memory Management Unit to translate the 16-bit (64KB) logical address space into a 26-bit (64MB) physical address space.
– a 16KB direct mapped cache to hide the SDRAM latency, using the FPGA internal block RAM
– a UART interface for external communications
He also ported CP/M-2.2, MP/M-II and UZI (a UNIX system) to the computer. His project is completely open-source and all the source code can be downloaded at the end of [Will]’s write up.
Thanks [hamster] for the tip.
The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.
The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.
[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl’s] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.
[Carl’s] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED. By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.
[Image via Wikimedia Commons]
A necessary tool for embedded development is a device that can talk common protocols such as UART, SPI, and I2C. The XC6BP is an open source device that can work with a variety of protocols.
As the name suggests, the XC6BP is a clone of the Bus Pirate, but based on a Xilinx Spartan-6 FPGA. The AltOR32 soft CPU is loaded on the FPGA. This is a fully functional processor based on the OpenRISC architecture. While the FPGA is more expensive than a microcontroller, it can be fully reprogrammed. It’s also possible to build hardware on the FPGA to perform a variety of tasks.
A simple USB stack runs on the soft CPU, creating a virtual COM port. Combined with the USB transceiver, this provides communication with a host PC. The device is even compatible with the Bus Pirate case and probe connector. While it won’t replace the Bus Pirate as a low-cost tool, it is neat to see someone using an open source core to build a useful, open hardware device.
Designing a computer from scratch is one of the holy grails of hardware design. For programmable logic, designing your own processor is a huge accomplishment. That’s exactly what [zhemao] has done. He created EZ8, an 8 bit processor is written in Verilog. EZ8 has a 3 stage pipeline, which makes design very interesting. Instruction set pipelines have been used in processors for many years. They speed up operation by allowing the processor to execute more than one instruction in parallel. The idea is similar to washing, drying and folding laundry. Most people pipeline their laundry. One load is in the washer, another in the dryer, and a third is being folded. Pipelines aren’t a free lunch though – there are hazards. If one instruction requires the result of an instruction which is still being executed in parallel, there’s a problem. In our laundry analogy this would be like having one sock on the folding table while its mate is still in the dryer. The folding operation must wait for the drying operation to complete before the socks can be paired. This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.
[zhemao] didn’t just give us a processor and no support though. He also included an assembler written in OCaml, and an emulator written in C. Several test assembly programs are also up on [zhemao’s] github repo to verify operation. [zhemao] has tested his processor with Altera Cyclone 5 series FPGAs, but it should be possible to port it to other FPGA manufacturers. If you want more information, [zhemao] also has a discussion going on in the ECE subreddit.
[Thanks for the tip LongHornEngineer!]
[Image courtesy of intel]
[Valentin] recently tipped us about an FPGA development board he just finished. It is called the FleaFPGA and is aimed to get people interested in the world of Field Programmable Gate Arrays. One of the other reasons that also got [Valentin] to design his own board was that he was frustrated with the existing solutions, them being either too pricey or fairly spare in terms of connectivity.
The main components that you can see in the platform shown above are: a lattice MachX02-7000HE FPGA (6864LUTs), 256Mbits of SDRAM, a USB2.0 host port, a 4096-color VGA connector, a 3.5mm stereo connector, an SD/MMC card slot, a PS/2 keyboard/mouse combo port, a few push buttons and LEDs. An expansion header is also present in order to connect the FleaFPGA to future shields that will be developed. Unfortunately only the board schematics have been released and [Valentin] is currently aiming for a price of $60 per board for <100 quantities. You’ll be able to see a video of the board in action after the break, in which the FPGA has been loaded with a 68000 software core running a variation of the Amiga Juggler Demo.
Continue reading “Introducing the FleaFPGA Experimenter’s Board”
Flip-flops are extremely simple electronic circuits, forming the basis of clock circuits, memory circuits, buffers, and shift registers. Through his dilly-dallying with digital logic, [Jeffrey] decided he would build his own. Not with Verilog or VHDL, though, but Migen: the Python-based way to build digital circuits with software.
Migen is an interesting tool that makes traditional FPGA programming a lot easier; instead of Verilog or VHDL, Migen allows an FPGA to be programmed in Python. Yes, it’s the tool you’ve been waiting for, and the tutorials make it look pretty easy. After installing Migen, [Jeff] wrote a class for a D flip-flop in only three lines of code. That’s three readable lines of code, and he was able to simulate the flip-flop with gtkwave in another two lines. Compared to learning the complexities of VHDL or Verilog, Migen makes digital logic and FPGA programming a breeze.
[Jeff] has a great tutorial for building a D flip-flop with Migen, but we’d love to see some more complex examples of what can be done with this very cool tool. If you’re building (or have built) something with Migen, be sure to send it in and relate your experiences.