Building new, weird CPUs in FPGAs

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The popularization of FPGAs for the hobbyist market means a lot more than custom LED controllers and clones of classic computer systems. FPGAs are also a great tool to experiment with computer architecture, creating new, weird, CPUs that don’t abide by the conventions the industry has used for 40 years. [Victor] is designing a new CPU that challenges the conventions of how to access different memory locations, and in the process even came up with a bit of example code that runs on an ARM microcontroller.

Most of the time, the machine code running on your desktop or laptop isn’t that interesting; it’s just long strings of instructions to be processed linearly. The magic of a computer comes through comparisons, an if statement or a jump in code, where the CPU can run one of two pieces of code, depending on a value in a register. There is the problem of reach, though: if a piece of code makes a direct call to another piece of code, the address of the new code must fit within an instruction. On an ARM processor, only 24 bits are available to encode the address, meaning a jump in code can only go 16 MB on either side of its call. Going any further requires more instructions, and the performance hit that comes along with that.

[Victor] decided a solution to this problem would be to create a bit of circuitry that would be a sliding window to store address locations. Instead of storing the literal address for jumps in code, every branch in the code is stored as a location relative to whatever is in the program counter. The result is an easy way to JMP to code very far away in memory, with less of a performance hit.

There’s an implementation for this sliding window token thing [Victor] whipped up for NXP’s ARM Cortex M3 microprocessor, and he’ll be working on an implementation of this concept in a new CPU over on his git.

Pumping 1080p video out of an FPGA

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[Hamster] admits this 1080p HDMI hack for an FPGA doesn’t put a signal that’s fully up to specifications. But as you can see in the image above it does output a 1920×1080 image at 60 Hz, which is the size and frequency of full HD video. It falls just short due to some jitter, which may be just fine if this is only being used for early prototyping and will be replaced with a dedicated encoder later in the design process.

Here he’s chosen a Pipistrello board but thinks that any device which has a Spartan 6 chip with the differential pairs connected to an HDMI socket will work. The difficulty of the task comes in serializing four output channels at 1500 Mb/s each. Because of this just coding your logic isn’t going to work. After roughing out the design [Hamster] went back in and chose to manually place some of the components to ensure that data from each channel arrives at the same time.

While you’re messing with HDMI you may also want to give this overlay hack a try.

A Bitcoin mining example for the BeagleBone with an FPGA shield

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If you’ve got a BeagleBone and an FPGA board you should give this Bitcoin mining rig a try. The hardware uses brute-force to solve hashes, looking for the rare sets that can be used as digital currency. This particular example is designed for the LOGi-bone which is an FPGA shield for the BeagleBone. But we don’t see anything that would make this difficult to use with other FPGA hardware.

We’ve seen FPGA hardware bitcoin mining in the past. It doesn’t offer as much horsepower as an array of GPUs would, but the ARM/FPGA combo can be used in a cluster in order to speed up the process. This sounds like a fun group project to take on at the local Hackerspace.

Stuffing an NES into an FPGA

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When the developer of the µTorrent torrent client and the ScummVM  LucasArts adventure game interpreter gets bored, something cool is bound to happen. Luckily for us, [Ludde] was a bit listless over Christmas, and with more time than energy to burn, implemented a Nintendo Entertainment System on an FPGA dev board.

The NES was powered by a Ricoh 2A03 CPU, a chip nearly identical to the 6502 found in the Commodore 64s and Apple IIs of the early 1980s. There are a few differences between the two, though: the NES CPU includes an Audio Processing Unit on the chip and is connected to a very cool Picture Processing unit elsewhere on the NES. [Ludde] put all these chips in his Spartan-6 FPGA with a lot of Verilog code.

The rest of the system – the RAM, display output, and controller input comes from the peripherals attached to the FPGA dev board. [Ludde]‘s specific board didn’t have a good digital to analog converter, so the composite output was traded for a VGA output. It’s not a completely accurate color pallet, but it’s still an amazing piece of work for someone who was simply bored.

Ask Hackaday: We might have some FPGAs to hack

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[Chris] is an IT guy for a medical clinic up in Alaska, and until very recently the systems he monitored, fixed, and beat with a wrench included over 100 Pano Logic “Zero Client” thin clients. Pano Logic just went out of business and all support for these little boxes have been cut off, leaving [Chris] with a hundred or so very interesting pieces of hardware.

The idea behind these “zero clients” is the ideal of a thin client – take all the storage, processing, RAM, and other goodies and move them to a server. Pano Logic took this one step further than other thin clients, removing the CPU, memory, and basically everything you’d find in a thin client. What was left was a Spartan-6 FPGA, a few chips to drive the USB ports, a pair of HDMI chips, and a few DDR2 modules. Basically, [Chris] has about 150 FPGA dev boards just sitting in a storage room. The only thing that is needed is a bunch of software and an extreme amount of cleverness.

After opening one of these zero clients, [Chris] found a Spartan-6 FPGA right next to what he thinks is a 6-pin programming port. Along with the FPGA are a few other chips that would make any FPGA dev board a very neat tool:

We’re going to agree with [Chris] these Pano Logic zero clients show a lot of potential. If you’re up to the challenge of creating a very, very cheap FPGA dev board out of some discarded hardware, head on over to ebay or chat up your local IT guy.

Breadboard friendly FPGAs

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Regular Hackaday readers will be familiar with all the cool things you can do with FPGAs; emulating old video game consoles, cracking encryption protocols, and DIY logic analyzers become relatively simple projects with even a modest FPGA dev board on your workbench. Many FPGA boards aren’t geared towards prototyping, though, and breadboard friendly devices are hard to come by. Here’s a pair of breadboardable FPGAs we’ve found while searching for some related hardware over the past few days

First up is the Mercury FPGA Module. Packaged in a DIP-64 format, the Mercury features a Spartan-3A FPGA with the equivalent of 200k logic gates. Elsewhere on the board is 512kB of RAM and 128kB of Flash storage. There are enough GPIO pins for nearly any project, but sadly only a 10-bit ADC – the same resolution you’d find in an AVR or PIC ‘micro.

Of course the Mercury isn’t the only breadboard-friendly FPGA dev board out there. There’s also the slightly more capable XuLA2 board powered by a Spartan-6 with 32 MB of RAM, 1MB of Flash. Unlike the Mercury, the XuLA2 can also fit in one of those ‘half-sized’ solderless breadboards.

Yes, it’s a different form factor than the commonly recommended Papilio One or the DE0. If you can suggest any other ‘beginners’ (i.e. doesn’t cost an arm and a leg) FPGA boards, leave a note in the comments and we’ll summarize them in another post.

Discrete FPGA will probably win the 7400 logic competition

For this year’s 7400 logic competition, [Nick] decided to build an FPGA out of logic chips.

Perhaps a short explanation is in order to fully appreciate [Nick]‘s work. The basic component of an FPGA is a slice, or cell, that performs boolean operations on its input and sends the result on its output. The core of these slices is a lookup table – basically a truth table that stores the result of every possible input combination.

One very easy way to implement a lookup table is to use a RAM or EEPROM chip. By tying the address lines of an EEPROM to the input and the data lines to the output, it’s possible to create a single slice of an FPGA very easily.

Unfortunately for [Nick], 74-series memories have long been out of production. There is another option open, though: shift registers. A shift register is basically an 8-bit memory chip with parallel inputs, so combining a shift register with an 8-input multiplexer is a very simple way to implement a 3-input, 1-output FPGA slice.

After figuring out how to tie these slices to bus lines, [Nick] needed a way to program them. Verilog or VHDL would border on insanity, so he wrote his own hardware description language. It’s certainly not as powerful or capable as the mainstream solutions to programming an FPGA, but it’s more than enough.

In the video after the break, you can see [Nick]‘s overview of his very large 8-slice FPGA while he runs a combination lock and PWM program. All the code, schematics, and board layout are up on [Nick]‘s git if you’d like to build your own.
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