Winning the Console Wars – An In-Depth Architectural Study

From time to time, we at Hackaday like to publish a few engineering war stories – the tales of bravery and intrigue in getting a product to market, getting a product cancelled, and why one technology won out over another. Today’s war story is from the most brutal and savage conflicts of our time, the console wars.

The thing most people don’t realize about the console wars is that it was never really about the consoles at all. While the war was divided along the Genesis / Mega Drive and the Super Nintendo fronts, the battles were between games. Mortal Kombat was a bloody battle, but in the end, Sega won that one. The 3D graphics campaign was hard, and the Starfox offensive would be compared to the Desert Fox’s success at the Kasserine Pass. In either case, only Sega’s 32X and the British 7th Armoured Division entering Tunis would bring hostilities to an end.

In any event, these pitched battles are consigned to be interpreted and reinterpreted by historians evermore. I can only offer my war story of the console wars, and that means a deconstruction of the hardware.

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Discrete Transistor Computer Is Not Discreet

Every few years, we hear about someone building a computer from first principles. This doesn’t mean getting a 6502 or Z80, wiring it up, and running BASIC. I’m talking about builds from the ground up, starting with logic chips or even just transistors.

[James Newman]’s 16-bit CPU built from transistors is something he’s been working on for a little under a year now, and it’s shaping up to be one of the most impressive computer builds since the days of Cray and Control Data Corporation.

The 10,000 foot view of this computer is a machine with a 16-bit data bus, a 16-bit address bus, all built out of individual circuit boards containing single OR, AND, XOR gates, decoders, multiplexers, and registers.  These modules are laid out on 2×1.5 meter frames, each of them containing a schematic of the computer printed out with a plotter. The individual circuit modules sit right on top of this schematic, and if you have enough time on your hands, you can trace out every signal in this computer.

The architecture of the computer is more or less the same as any 16-bit processor. Three are four general purpose registers, a 16 bit program counter, a stack pointer, and a status register. [James] already has an assembler and simulator, and the instruction set is more or less what you would expect from a basic microprocessor, although this thing does have division and multiplication instructions.

The first three ‘frames’ of this computer, containing the general purpose registers, the state and status registers, and the ALU, are already complete. Those circuits are mounted on towering frames made of aluminum extrusion. [James] already has 32 bytes of memory wired up, with each individual bit having its own LED. This RAM display will be used for the Game of Life simulation once everything is working.

While this build may seem utterly impractical, it’s not too different from a few notable and historical computers. The fastest computer in the world from 1964 to ’69 was built from individual transistors, and had even wider busses and more registers. The CDC6600 was capable of running at around 10MHz, many times faster than the estimated maximum speed of [James]’ computer – 25kHz. Still, building a computer on this scale is an amazing accomplishment, and something we can’t wait to see running the Game of Life.

Thanks [aleksclark], [Michael], and [wulfman] for sending this in.

VCF East: [Bil Herd] And System Architecture

Last Friday the Vintage Computer Festival was filled up with more than a dozen talks, too many for any one person to attend. We did, however, check out [Bil Herd]’s talk on system architecture, or as he likes to call it, the art and science of performance through balance. That’s an hour and fifteen minute talk there; coffee and popcorn protocols apply.

The main focus of this talk is how to design a system from the ground up, without any assumed hardware, or any specific peripherals. It all starts out with a CPU, some memory (it doesn’t matter which type), and some I/O. That’s all you need, whether you’re designing a microwave oven or a supercomputer.

The CPU for a system can be anything from a 6502 for something simple, a vector processor for doing loads of math, or have a RISC, streaming, pipelined, SIMD architecture. This choice will influence the decision of what kind of memory to use, whether it’s static or dynamic, and whether it’s big or little endian. Yes, even [Bil] is still trying to wrap his head around endianness.

MMUs, I/O chips, teletypes, character displays like the 6845, and the ANTIC, VIC, and GTIA make the cut before [Bil] mentions putting the entire system together. It’s not just a matter of connecting address and data pins and seeing the entire system run. There’s interrupts, RTCs, bus arbitration, DTACK, RAS, and CAS to take care of that. That will take several more talks to cover, but you can see the one last Friday below.

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RISC, Tagged Memory, and Minion Cores

Buy a computing device nowadays, and you’re probably getting something that knows x86 or an ARM. There’s more than one architecture out there for general purpose computing with dual-core MIPS boards available and some very strange silicon that’s making its way into dev boards. lowRISC is the latest endeavour from a few notable silicon designers, able to run Linux ‘well’ and adding a few novel security features that haven’t yet been put together this way before.

There are two interesting features that make the lowRISC notable. The first is tagged memory. This has been used before in older, weirder computers as a sort of metadata for memory. Basically, a few bits of each memory address tag each memory address as executable/non-executable, serve as memory watchpoints, garbage collection, and a lock on every word. New instructions are added to the ISA, allowing these tags to be manipulated, watched, and monitored to prevent the most common single security problem: buffer overflows. It’s an extremely interesting application of tagged memory, and something that isn’t really found in a modern architecture.

The second neat feature of the lowRISC are the minions. These are programmable devices tied to the processor’s I/O that work a lot like a Zynq SOC or the PRU inside the BeagleBone. Basically, they’re used for programmable I/O, implementing SPI/I2C/I2S/SDIO in software, offloading work from the main core, and devices that require very precise timing.

The current goal of the lowRISC team is to develop the hardware on an FPGA, releasing some beta silicon in a year’s time. The first complete chip will be an embedded SOC, hopefully release sometime around late 2016 or early 2017. The ultimate goal is an SOC with a GPU that would be used in mobile phones, set-top boxes, and Raspi and BeagleBone-like dev boards. There are enough people on the team, including [Robert Mullins] and [Alex Bradbury] of the University of Cambridge and the Raspberry Pi, researchers at UC Berkeley, and [Bunnie Huang].

It’s a project still in its infancy, but the features these people are going after are very interesting, and something that just isn’t being done with other platforms.

[Alex Bardbury] gave a talk on lowRISC at ORConf last October. You can check out the presentation here.

Geodesic Structures that aren’t just Domes

Geodesic structures

[Brian Korsedal] and his company Arcology Now! have developed a great geodesic building system which makes architectural structures that aren’t just limited to domes. They 3D scan the terrain, generate plans, and make geodesic steel space frame structures which are easy to assemble and can be in any shape imaginable.

Their clever design software can create any shape and incorporate uneven terrains into the plans. The structures are really easy to construct with basic tools, and assembly is extremely straight forward because the pole labels are generated by the design software. Watch this construction time lapse video.

At the moment, ordering a structure fabricated by the company is your only option. But it shouldn’t be too hard to fabricate something similar if you have access to a hackerspace. It may even be worth getting in touch with Arcology now! as they do seem happy collaborating to make art like the Amyloid Project, and architectural structures for public spaces and festivals like Lucidity. Find out what they are up to on the Arcology Now! Facebook page.

Would this be perfect for what you’ve been thinking about building? Let us know what that ‘something’ is in the comments below. Continue reading “Geodesic Structures that aren’t just Domes”

DUO 128 Elite, 4 bit CPU

We’re not sure how we missed [Jack Eisenmann’s] 4 bit TTL CPU when we were tipped off the first time, but we’re glad it was sent in again for us to feature it.

41 different ICs (mostly TTL) come together to comprise the DUO 128 Elite. While the architecture is a little different than what we’ve seen before, using “nyckles”, the DUO 128 Elite still works perfectly. Catch a video of some example programs, including pong, after the divide.

[Thanks Marc G-C]

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Breathing Walls with Shape Memory Alloy Wire

When you need something quietly bending or moving, don’t underestimate SMA’s (or Shape Memory Alloys). The Living Glass project by architects [David Benjamin] and [Soo-in Yang] catalogs an experiment in building interactive, flexible, “breathing”, walls out of SMA wire and microcontrollers. Although they use Basic Stamps, the project could easily be extended to more cost-effective microcontrollers for large surfaces. The project is well documented with videos (AVI) of each prototyping step and even includes the ideas that were ultimately scrapped. Even if you don’t build a wall of interactive gills, this project should give you plenty of ideas for uses of SMA wire embedded in semi-flexible materials.