[Andrea] built this LED chaser using one logic chip. It illuminates all but one of the six LEDs, with the dim bit moving back and forth along the row in a chase sequence. This is something like an inverse Larson Scanner without the fading tail. But doing it with a logic chip instead of a microcontroller is a fun challenge.

Which brings us to the point of this feature. [Andrea] didn’t really post an explanation of how the circuit works. Usually missing details mean that we archive the tip and move on to the next one, but we think this provides a fun activity. Can you figure out how the circuit works? We already know that it’s using a CD4017 decade counter/divider chip. This gets its clock signal from a 555 timer circuit. [Andrea's] schematic is a bit hard to read, but grab a copy, blow it up a bit (or use your browser zoom) and study the CD4017 datasheet (PDF) if you need to.

Want proof that it does actually work? It’s embedded after the break.

We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES controller for input. So far it sounds like a very normal version of the game. But as you start to hear how it works in the presentation after the break you fall in love with what’s going on here.

First of all, it’s not written in VHDL — the predominant programming language for FPGAs. Instead, [Darrell] used the schematic-only approach to build the logic. Okay, that’s starting to get more interesting. As he continues to explain the circuit we get to see how the control input works (pretty simple since the SNES controller uses a parallel-to-serial shift register) and how the display is multiplexed. But the actual game logic is where things really take off. Each pixel in the display has its own individual logic circuit. Basically every cell is its own processor which reacts both to what is passed into it, as well as to a random seed. That seed system is called the ‘bucket brigade’ and passes a chance to spawn a piece of food from one cell to the next. All of this together makes for one simple game that is eloquently executed.

[74hc595] just finished his entry in the 7400 logic contest. It’s a drum machine built entirely from 7400-series logic chips. He hasn’t quite reached full completion of the project yet. The hardware works just fine, and he’s built a foam core face plate with many more controls than you see here but much of the circuit is still on a breadboard at this point and only two of the channels have been complete thus far.

Jump to the video clip after the break to get the details of how the system works and to hear it in action. This demonstration is one of the best we’ve seen for a synthesizer project as he actually talks about what each control does, and how that is accomplished with the hardware. We’re not going to go into detail about the circuitry he’s designed. As we said before, it uses 7400 logic but also sources a 555 timer to keep the beat. The page linked above has a PDF of the schematic available and you could really lose a lot of time studying how he did this. We might even try to build it in a simulator to see what we can learn.

[Caleb] is hard at work on a driving game based on 7400 series logic chips. This will be his entry in the Open 7400 Logic Competition, and it really outlines why this contest is especially tricky.

The concept behind the game is quite simple. You’re the driver of a car (the red dot at the bottom of the display square seen above) and need to navigate the curves in the road as you drive along. It’s the same game as we saw played on receipt paper back in June. [Caleb's] using and LED matrix as the display, and we’re confident that if we grabbed our favorite microcontroller we could have this up and running on an 8×8 bi-color display in an afternoon. But doing it without the crutch of a programmable chip really brings out the clever engineer inside of you.

The circuit seen above is a Logisim proof-of-concept that [Caleb] went on to test on the breadboard. He thought he had everything figured out until he realized that his Data Flip-Flops were very occasionally not powering up in the same state as he predicted. Don’t worry, he found a solution to the problem. But we can’t wait to see what other hurdles he encounters as he pushes on toward completing the project.

Here’s another chance to ply your hacking skills for cash and prizes. Dangerous Prototypes has just announced the Open 7400 Logic Competition. First prize is $100 and a bunch of hacking goodies. But even better is that since it was announced, more sponsors have stepped up to increase the kitty, and the number of entries that will get prizes.

The parameters for entry are wide open. You can design anything you want, with emphasis on originality. Make sure you take plenty of pictures and document the project along the way. Their judging will take into consideration the amount of detail posted about the project (hence the ‘Open’ in the contest title).

Need some ideas to get you started? We enjoyed the useless machine that used a 7400 NAND gate. You could always build a time piece of some sort like this no-microcontroller clock. Perhaps hardware control like this stepper motor driver is more to your liking?

[Thanks Moderboy]

[Osgeld] built himself a binary clock. He didn’t take the time to explain his project, but he did post beautifully hand-drawn schematics and pictures of the circuit (PDF) as he was building it. We’ve seen clock projects that use mains frequency as the clock source and that’s the route that [Osgeld] chose for his build. He started with a 9-12V AC wall wort as a power input. From there it’s just a matter of using a bridge rectifier to convert to DC, then a 7805 linear regulator to establish a steady 5V rail. A resistor and a couple of diodes allow him to pull the 60 Hz frequency off of the incoming AC, and then use a combination of 4000 and 7400 logic chips to count the pulses and keep track of the time.

Lazarus-64, breadboard game system; certainly sounds like something from the 1980s. We were surprised to find out not only the name, but also all the ICs used are only those available from the retro age of 30 years back (Save for the AVR controlling everything, of course). Even more amazing is how it has 256 flicker free color support, while not using NTSC chips. Which Goes to show that even if there are common solutions out there for cheap, building or compiling your own is not necessarily a bad thing or a waste of time.

There is a whole lot more to Lazarus, including double buffering and VMS, but sadly it appears progress has stopped on the Lazarus-64 breadboard game system, with the last update being last year. But we can still bask in the amazing glow that currently is.

the folks over at OpenSchemes are at it again. This time they’ve cracked open a low end ZerPlus logic analyzer and modified it to function the same as the higher end model. The 16 channel version they purchased appeared to be fully capable of handling the 32 channels of the more expensive model. The installation of the additional components looks like it might be somewhat difficult, but it is certainly cheap.We love seeing things upgraded for cheap. You might recognize OpenSchemes from when they upgraded the DMM tweezers or hacked the USB serial adapters.

[via HackedGadgets]

[Jack Gasset] sends in the logic analyzer he’s been working on. The logic analyzer boasts an impressive array of features, it can sample 32 channels at 100MHz, 16 channels at 200MHz, SPI, UART, I2C and more. The analyzer’s maximum sample size is 4K for now, and it supports RLE to reduce the memory consumed. The analyzer connects to a java client on a standard PC via USB. The open source hardware based on a Xilinix FPGA can be purchased pre-assembled for $100 which makes it a direct competitor for the Salea logic analyzer we reviewed earlier this year.

A logic analyzer records bus communications between two chips. If you’ve ever had a problem getting two chips to talk, or wanted to reverse engineer a protocol, a logic analyzer is the tool you need to spy on the bus.

The Logic is a USB logic analyzer with eight channels and sampling rates up to 24MHz. Among hobby-level logic analyzers, the Logic has a good mix of features and decent sampling rates. We’ve been following Joe Garrison’s work on the Logic for a long time. If you’ve ever considered bringing a product to market, you can learn a lot from Joe’s blog that documents his development process.

When it debuted, the Logic was so popular that it was hard to buy one. It’s now widely available, and Saleae gave us one to try. Read our review below.

Logic Analyzers vs. Oscilloscopes

Most modern electronics projects will benefit more from a logic analyzer than an oscilloscope. An oscilloscope displays a graph of an analog voltage as it varies over time, such as the curve of a sine wave. A logic analyzer only detects high and low digital states, but it records many signals simultaneously. Logic analyzers dump data to a computer for analysis, very few oscilloscopes have this feature.

What you get

The Logic comes packaged in an external hard drive case. The analyzer is a small, anodized aluminum puck with laser etched signal markers. It’s much smaller than we expected, slightly smaller than a compact flash storage card. A mini-B USB cable is included.

A heavy-gauge cable and nine E-Z-Hooks (5 shown) connect the Logic to a circuit. The hooks are a really nice touch; press the back of the hook to expose a pair of tweezers, grab onto a signal wire, and retract to hold it in place. The retractable tweezers prevent accidental shorts on cramped test circuits.

Software isn’t included, instead you get instructions to download the latest version from the Saleae web site. We always download the latest software, so we appreciate that there’s one less CD headed to the landfill.

Right now, only Windows XP/Vista software is available, but Mac and Linux software should be ready soon. Warning: the Windows version requires .NET 3.5, download the redistributable off-line installer if you don’t want to give internet access to Microsoft’s online installer.

Using it

Using the Logic is simple. Connect the gray ground wire to the ground of the test circuit, then hook into the signal lines you want to record. We connected it to the 32K SPI SRAM that we demonstrated earlier this week. SPI has four important signals; enable, data in, data out, and clock. The E-Z-Hooks make it dead simple to tap into the signals without accidental shorts.

Be mindful of wire orientation. We associate a black wire with ground, but the Logic cable uses gray. Comments on SparkFun’s product page suggest that reversing the connections will damage the Logic.

The software analyzes and displays signal captures. The primary configuration options are the sampling rate (200KHz-24MHz) and number of samples (millions to billions). We were able to sample at 24MHz, but the top speed depends on how much other stuff is using the USB bus. A 24MHz sampling rate can capture signals up to 12MHz, we found this suitable for all the protocols we use. The total number of samples is limited only by the available PC RAM.

There’s a four level trigger that watches the signals, and waits for a specific combination before it starts recording samples.  Since we’re analyzing SPI, the most logical place to start capturing is when the SPI enable signal drops at the beginning of a bus transaction. We set the Logic trigger to start sampling when SPI enable is 0 by changing its trigger to ’0′.

We really like the profiles that decode most common serial protocols; 1-Wire, I2C, SPI, and asynchronous serial.  CAN and other protocols will be added eventually.

Profiles suggest names for each signal, and convert squiggly lines into readable byte values. This is a really awesome feature. Without it, you’d have to count clock pulses to identify byte boundaries, and then manually decode the values.

This transaction shows the host issue the read configuration register command (0×05), and the SRAM response (0×41).

We also tried the 1-Wire decoder with a DS2431 EEPROM. The software identified the 1-Wire reset command, and the 1-Wire ‘search rom’ command (0xf0).

A look inside

The Logic is based on the Cypress Semiconductor CY7C68013A-56PVXC, an Intel 8052 microcontroller with a USB peripheral. The 8052 is an enhanced version of the well-known 8051. We can also identify a 24MHz crystal, which is probably multiplied to 48 or 96MHz by an internal phase-locked loop.

Conclusion

Logic analyzers take the guess work out of debugging inter-chip communication. If you can’t see what’s going on, the best you can do is guess about the problem. When a project won’t work, 99% of the time we can solve the problem immediately by looking at the signals with a logic analyzer. Without it, there’s no easy way to know what’s happening.

The Logic records 8 channels at 24MHz. The Windows software has useful features, and there’s an SDK if you want to write your own apps. Linux and Mac versions are under development. We really like this logic analyzer, and plan to use it to illustrate future articles.

The Logic is $149 at the Saleae website and SparkFun, and Joe is working on EU distribution. If you’re interested in the Logic, but aren’t ready to buy, you can download the software and try it in demo mode.

Hack a Day review disclosure: We asked for a Logic and Saleae sent it to us

We love old display technology, like Nixie tubes, but they’re often difficult to work with because they require higher voltages than digital logic. Vacuum florescent displays (VFD) fall into this category. While not necessarily “old”, they are becoming far less common than LCDs. The main benefit of a VFD is that it actually produces light directly; it doesn’t require a backlight. You’ll find these displays on various players and appliances: CD, DVD, VCR, microwaves, stoves, car headunits, and others.

[Sprite_tm] had written off some VFDs, but recently revisited them with renewed interest. He started by testing what sort of voltage would be required to drive the display. It took 3V for the filament plus 15V to drive the grids. There are VFD controller chips available, but he wanted to get this working with what he had on hand. He had experience with older 40xx series logic, which can be powered by much higher voltages than 5V 74xx. His final schematic has three 4094 serial to parallel chips with an ATtiny2313 controller. A 5V power supply is dropped to 3V with diodes to drive the filament while a boost converter brings it up to 15V for the 4094s that switch the segments. While the code is specific to this display, it would be a great place to start your own project.

Complex programmable logic devices (CPLDs) contain the building blocks for hundreds of 7400-serries logic ICs. Complete circuits can be designed on a PC and then uploaded to a CPLD for instant implementation. A microcontroller connected to a CPLD is like a microcontroller paired with a reprogrammable circuit board and a fully stocked electronics store.

At first we weren’t sure of the wide appeal and application of CPLDs in hobbyist projects, but we’ve been convinced. A custom logic device can eliminate days of reading datasheets, finding the ideal logic IC combination, and then waiting for chips to arrive. Circuit boards are simpler with CPLDs because a single chip with programmable pin placement can replace 100s of individual logic ICs. Circuit mistakes can be corrected by uploading a new design, rather than etching and stuffing a new circuit board. CPLDs are fast, with reaction times starting at 100MHz. Despite their extreme versatility, CPLDs are a mature technology with chips starting at $1.

We’ve got a home-etchable, self programming development board to get you started. Don’t worry, this board has a serial port interface for working with the CPLD, and doesn’t require a separate (usually parallel port) JTAG programmer.

Intro to CPLDs

When to use a CPLD

Consider using a CPLD when a design calls for more than one 7400 series logic ICs. A CPLD will be cheaper, faster, and can be programmed with your ideal pin-out configuration for simpler PCBs.

Use a CPLD in tricky designs that might require several iterations. It’s easier to design a new circuit in software and upload it to the CPLD than it is to design, etch, and stuff a new circuit board.

For maximum speed and instant response, choose a CPLD. The difference in speed is amazing; CPLDs start at a 100MHz, while microcontrollers respond to interrupts at a few MHz. CPLD designs form circuits that react to external stimulus, reactions occur almost instantaneously. A microcontroller executes code to react to events, even interrupt routines have comparatively high latency.

CPLD vs FPGA

FPGAs are better known than CPLDs, but they share many characteristics. This analogy isn’t perfect, but we like it: where FPGAs are a reprogrammable processor core, a CPLD is a reprogrammable circuit board or breadboard. FPGAs replace microcontrollers, memory, and other components. CPLDs absorb logic ICs, and work well with a microcontroller.

Manufacturers

Altera and Xilinx, the biggest CPLD manufacturers, are better known for their FPGAs. Lattice Semiconductor is another large CPLD manufacturer with less community following. Atmel makes pin-compatible versions of old industry-standard CPLDs.

If you plan to work at 5volts, your options are limited. Xilinx XC9500 CPLDs are still available as new old stock, but cost four times more than newer 3.3volt equivalents. Atmel’s ATF1502 series works at 5volts, but they don’t offer a free development environment.

At 3.3volts there’s more options, but new CPLDs increasingly have a core that runs at 2.5volts, 1.8volts, or lower. The Altera MAXII and the Xilinx XC9500XL series are probably the most popular 3.3volt CPLDs. Xilinx also makes the CoolrunnerII CPLD, but it only comes in a TQFP package and requires a separate 1.8volt supply for the core.

Packages

Most manufacturers offer one or two CPLDs in a hobbyist friendly PLCC 44 package, though this is starting to disappear. PLCC is an SOIC-sized surface mount chip with pins on all four sides. PLCC44 sockets are commonly available in through-hole and SMD versions. Unfortunately, newer CPLD families are starting to eliminate the PLCC package and offer only 44 pin and larger TQFP chips, such as Xilinx’s CoolrunnerII.

Development environments

Most manufacturers offer a free development environment that supports design entry using simple schematics, as well as Verilog or VHDL. Many won’t support the latest FPGAs in the free version, but we only need the CPLD parts anyway. Altera has Quartus, Xilinx has ISE, and Lattice has ispLever. Atmel has ProChip Designer for the ATF15xx series, but they only offer a 6month trial license — which they wouldn’t actually give us.

Programmers

The development board we present doesn’t need a separate JTAG programmer because the PIC microcontroller already programs the CPLD.  If you want an external programmer, the cheapest are the parallel port programmers: Parallel Cable III for Xilinx and BytleBlaster for Altera. Inexpensive clones, and schematics, are available at SparkFun.  The OpenOCD is a generic USB JTAG programmer that will work with many CPLDs, FPGAs, and ARMs.

Our choice

We eventually settled on the Xilinx XC9500XL series because it had a cheap development kit we could use to test our JTAG programmer prior to implementing an entire design.

The DO-CPLD-DK from Digilent includes a XC9572XL, a CoolrunnerII, and parallel port programmer. Nu Horizons has some old non-ROHS models for $40, but due to sloppy variable type handling in their credit card processing scripts, we couldn’t complete an order online. We tried to do it over the phone but they refused to take such a small order on the phone, even during a website malfunction. In the end, it was cheaper to pay full price at Digikey (#122-1512-ND) after including New Horizon’s exorbitant shipping charges. We wouldn’t normally mention this, but with only two places to buy the board it’s probably worth noting our experience.

CPLD development board

Click here for a full size schematic image (PNG). The circuit and PCB are designed using the freeware version of Cadsoft Eagle. All the files for this project are included in the project archive linked at the end of the article.

Circuit

A PIC 24FJ64GA002 microcontroller (IC1) provides the user and programming interface to the CPLD. We use this $4 PIC in a lot of projects because the peripheral pin select feature makes board routing really easy. Check out our introduction to the PIC24F for more details. The PIC needs to communicate with a PC serial port, so we added an inexpensive MAX3232 RS232 transceiver. The serial interface should work with a USB->serial adapter.

Our choice of CPLD (IC3), a Xilinx XC9572XL (PDF), is connected between the PIC and several other components. We can create an endless variety of circuitry between the PIC and other chips using the reprogrammable logic inside the CPLD. The PIC will program the CPLD with code sent from a PC serial port, but we still brought the JTAG pins to a header for easy external debugging.

A DS1085 digital programmable oscillator (IC4) generates clock frequencies between 8KHz and 133MHz, at 10KHz increments. This is very similar to the DS1077 we covered earlier, but it has even steps between all frequencies. The DS1085 requires a 5volt supply (VR2). The I2C interface also runs at 5volts, so we connected it to 5volt tolerant PIC pins. It’s possible to use the 3.3volt 66MHz 1085L instead, and remove the 5volt supply.

We used a cheap 3.3volt SOT223 voltage regulator (VR1) to power most of the circuit.  The 5volt supply (VR2) can be excluded if you use a slower 1085L 3.3volt oscillator.

CPLDs are commonly used as a memory controller, so we included 32K of SRAM (IC5) on the development board. A 3.3volt latch with 5volt tolerant inputs interface the memory inputs to a wide range of external voltages (IC6). The latch inputs are held low with a 1Mohm resistor network (RN1). We’ll discuss this section extensively in an upcoming article.

PCB

The board is a quasi one-sided design. We made several compromises so we could prototype this highly experimental PCB ourselves. We present the board ‘as is’ for other die-hards that might want to etch this board at home. If you send the PCB to a board house, try to correct these issues prior to producing a ‘real’ double-sided board.

One power pin of the CPLD is missing a decoupling capacitor entirely; there was no way to put a capacitor in that area. One CPLD decoupling capacitor, and the SRAM decoupling capacitor, are through-hole parts. Using these through-hole parts eliminated a few jumper wires.

The jumper wires on the back of the board are optimized for single-sided production, rather than good design practices. We faked a double-sided board by soldering the power bus on the back. A real double-sided board design should route the power bus to avoid crossing signal paths, and include the missing decoupling capacitors.

We used an surface mount PLCC chip socket, but a through-hole version is definitely a better idea. We though the SMD version would be easy to solder, but it turned out to be a nightmare. We really wanted the CPLD to be on the front of the board for the coolest possible presentation. A proper two-sided board with plated through-holes can have a through-hole socket on the front, but this wasn’t possible with our 1-sided prototype board.

Parts list

Click here for a full size placement diagram (PNG).

Firmware

The firmware is written in C using the free demonstration version of the PIC C30 compiler. Learn all about working with this PIC in our introduction to the PIC 24F series. The firmware is included in the project archive at the end of the article.

We wanted a super easy way to interact with the hardware on the board without endless compile-program-test cycles. We made a custom version of the Bus Pirate firmware that  provides a simple ASCII terminal interface to the DS1085 clock chip (I2C), the CPLD programing interface (JTAG), and a 3 wire (SPI) interface to the CPLD. Check out the Bus Pirate tutorial for background on the simple syntax used with the firmware.

The original Bus Pirate firmware handles several protocols that share the same pins. For the CPLD version, we changed the pin assignments to fit the connections on the development board. We also removed unused modules and options.

CPLD blinky LED examples

We prepared several designs in Xilinx’s ISE development environment. The schematics, pin placement files, and compiled designs (XSVF) are included in the project archive linked at the end of the article.  A full explanation of ISE is beyond the scope of this article; we found the help files sufficiently useful to make these examples.

The first design simply lights the LED connected to pin 8 of the CPLD.

Prepare the XSVF file

XSVF is a compressed JTAG programming format, as described by Xilinx in this application note (PDF). XSVF isn’t limited to programming Xilinx devices, and can be prepared for any chip that provides a common BSDL JTAG definition file.

Open the iMPACT programming tool from the ISE Design Suite project panel under Configure target device->iMPACT.

• Choose the option to create a boundary scan file,  and set the type to XSVF.
• Give the XSVF output a file name and then add a compiled CPLD image (ex1.jed) when prompted to add a device.
• You should see a JTAG chain that contains a single device.

Click on the device and choose program; iMPACT will record the programming sequences to an XSVF file.

With XSVF file in hand, it’s time to open up a terminal and program the CPLD. We like Tera Term and Hercules on Windows. You must enable XON/XOFF flow control in the client to use the JTAG interface. The default PC side setting for the development board terminal is 115200bps, 8N1.

HiZ>m <–select mode
1. HiZ
2. I2C
3. JTAG
4. RAW3WIRE
MODE>3 <–JTAG
900 MODE SET
602 JTAG READY
JTAG>(2) <–probe JTAG chain macro
xxx JTAG INIT CHAIN
xxx JTAGSM: RESET
xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Instruction Register (DELAYED ONE BIT FOR TMS)
xxx JTAGSM: IR->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAGSM: DR->IDLE
xxx JTAGSM: RESET
xxx JTAGSM: RESET->IDLE
xxx JTAGSM: IDLE->Data Register
xxx JTAG CHAIN REPORT:
0×01 DEVICE(S)
#0×01 : 0xC9 0×02 0×06 0x9A <–XC9572XL responds
xxx JTAGSM: DR->IDLE
JTAG>

In the terminal we enter the mode menu (m), and choose JTAG (3). Macro 2 probes the JTAG chain, in our case this is just the CPLD.  The chain report tells us that the chip is connected and responding. Read more about the JTAG interface.

Now we can run the XSVF programmer, macro (3), and upload the XSVF file from the terminal in binary mode. The first example just lights the LED on pin 8. If the LED lights, we can verify that programming was successful. If your LED doesn’t light, don’t despair; sometimes the JTAG programmer sticks and a reset macro (1) will get the chip going.

LED at full brightness.

74LS32/4071 OR gate, blink at half rate (/2)

A major component of the CPLD development board is the 1085(L) frequency synthesizer connected to pin 7 of the CPLD. The next example uses a logic OR gate, like a 74LS32 or 4071 IC, to blink the LED whenever the clock signal is high. At even the slowest clock rate the blinking will be too fast to see, but we should get a nice PWM dimming effect compared to the first example.

JTAG>m <–select mode
1. HiZ
2. I2C
3. JTAG
4. RAW3WIRE
MODE>2 <–I2C interface to DS1085
900 MODE SET
202 I2C READY
I2C>(1) <–address search macro
xxx Searching 7bit I2C address space.
Found devices at:
0xB0 0xB1 <–found the DS1085 address
I2C>

Program the CPLD as before, and then switch to I2C mode to access the DS1085 clock. We could look up the device address in the datasheet, but we save a few seconds by running the address search macro; the report tells us the chip answers to 0xb0 (write) and 0xb1 (read).

I2C>{0xb0 0×02 0b00011111 0b10000000}<–max prescaler
210 I2C START CONDITION
220 I2C WRITE: 0xB0 GOT ACK: YES
220 I2C WRITE: 0×02 GOT ACK: YES
220 I2C WRITE: 0x1F GOT ACK: YES
220 I2C WRITE: 0×80 GOT ACK: YES
240 I2C STOP CONDITION
I2C>{0xb0 1 0b11111111 0b11000000}<–max divider
210 I2C START CONDITION
220 I2C WRITE: 0xB0 GOT ACK: YES
220 I2C WRITE: 0×01 GOT ACK: YES
220 I2C WRITE: 0xFF GOT ACK: YES
220 I2C WRITE: 0xC0 GOT ACK: YES
240 I2C STOP CONDITION
I2C>

The DS1085 is almost exactly like the DS1077 we covered earlier, but has a DAC controlled oscillator for even steps between all frequencies. We programmed the clock to the slowest frequency using the commands shown above. The LED is dimmed by the pulse-width modulation effect of the clock signal.

LED at half brightness.

74F269 16bit synchronous counter, blink slowly (/65535)

We just programmed the CPLD with a logic OR gate similar to a 74LS32. Now, we’re going to reprogram the chip with a 16bit counter like two cascaded 74F269s.  At $1.15 each, two 74F269 Ics are more expensive than the XC9572XL CPLD. A 16bit counter rolls over once per 65535 ticks, so a LED attached to the last bit will toggle once every 65535/2 ticks.

Now we can see the cool part of CPLDs. The CPLD is like a programmable breadboard; we just popped out the 74LS32 and put in a 74F269, without buying parts, reading datasheets, etching, wiring, etc. A microcontroller connected to a CPLD can reconfigure its own circuit board to fix errors, add features, or re-purpose it for entirely different applications.

We upload the new design as before, but now the clock is divided by 65535 and the LED toggles about once per second.

Taking it further
Next time we’ll look at discrete 7400-series logic chips, and implement a ton of them in the CPLD to make a high-speed bus sniffer and logic analyzer.

Download: bitclone.v1.zip

“Triggers” are used to signal specific activity. On the PS2, one was attached to the falling signal on the slave select line. This event means the master is about to start sending data.

The final area worth exploring is “measurements”. These can be frequency or arbitrary time intervals between events. The Logicport has multiple ground connections to eliminate noise from the signal and you’ll have to play with sample rate and logic level to get things running smooth. It’s nice to see how-tos written from the perspective of someone just getting started with the tool.