For his A-level electronic course work, [Andrew] decided to build a digital sound recorder that doesn’t use a microcontroller.
[Andrew]’s build captures audio from an on board microphone at 8000 samples/second. The audio is digitized into 8-bit sound data and sent to an SRAM. The recording and playback functions are controlled entirely by 4000-series logic chips. He admits the sound quality is pretty poor; this is mostly due to the 8kHz sample rate. In some circles, though, a terrible sample rate is seen as being pretty cool so we’re not going to say [Andrew]’s build is useless.
There’s some pretty smart design choices in [Andrew]’s build, like a cut off filter on the microphone set at 4000 Hz (the Nyquist frequency of his system). For the recording medium, he used an SRAM that can hold about half a megabyte of data. At 8000 samples/second, [Andrew]’s build can store a little more than 60 seconds of audio. The build may not be a logic chip computer, but there’s not any question in our mind that [Andrew] learned something. Check out [Andrew]’s 66-page coursework report here (PDF warning).
How much memory do you really need? We suppose it’s not really our place to judge how you
misuse use memory in your projects. But we do appreciate the clean and orderly technique that [Eric Rogers] uses to add multiple SPI SRAM chips to an Arduino.
The heavy lifting is done with a CPLD shield called the Amani 64. It intercepts the SPI calls from the Arduino to an SRAM chip, and translates the address information to find the appropriate data on a collection of 23K256 devices. These chips are inexpensive, and using several of them provides a savings over choosing a single SPI addressable chip with a larger memory size.
The best part is that the flexibility of the CPLD allowed [Eric] to devise an addressing system that takes advantage of unused bits in the Arduino’s SPI data transfer functions. When using a single 23K256 chip, there are four write functions that waste a total of six bits. He devised a method to inject addressing data into these unused bits, allowing him to address up to 64 different memory chips for a potential of 2 MB of storage. The CPLD pulls out this injected address and subsequently writes or reads the bank of SRAM chips.
Looking for other SRAM upgrade options? Here’s another one that uses multiplexing to decrease the address lines necessary to add memory.
Those who are familiar with Atmel’s line of 8-bit AVR microcontrollers should already know that some of them have support for external RAM. But have you ever actually used this feature? We haven’t. Now you can learn how it’s done by reading through this guide. It touches on all of the hardware, but doesn’t dwell on it. Instead, you’ll get the background you need on how to write to, read from, and test an external module like the one sticking up in the image above. The test routine shows how to make sure everything’s working correctly with your memory mapping before you begin developing firmware around this increased capacity.
Microchip’s new 23K256 is a serially interfaced 32 kilobyte SRAM memory chip, available in 8 pin DIP and 8 pin SO packages. SRAM, like EEPROM, is a data storage medium. Data stored in SRAM is lost without constant power, but it’s really fast and there’s no limits to the number of write cycles. EERPOM stores data even without power, but it’s slow and usually limited to around a million write cycles.
32K SRAM chips typically have 15 address lines and 8 data lines, like the IS61LV256AL we used on our CPLD development board. The 23K256 requires just four signal lines, but sacrifices the speed of a parallel memory interface. It’s a great way to add extra memory to a low-pin count microcontroller without routing 23 signal traces. We’ll show you how to interface this chip below.
Continue reading “Parts: 32KB SPI SRAM memory (23K256)”