The guys over at hackshed have been busy. [Carl] is making programmable logic design easy with an 8 part CPLD tutorial. Programmable logic devices are one of the most versatile hardware building blocks available to hackers. They also can have a steep learning curve. Cheap Field Programmable Gate Arrays (FPGA) are plentiful, but can have intricate power requirements. Most modern programmable logic designs are created in a Hardware Description Language (HDL) such as VHDL or Verilog. Now you’ve got a new type of device, a new language, an entirely new programming paradigm, and a complex IDE to learn all at once. It’s no wonder FPGAs have sent more than one beginner running for the hills.
The tutorial cuts the learning curve down in several ways. [Carl] is using Complex Programmable Logic Devices (CPLD). At the 40,000 foot level, CPLDs and FPGAs do the same thing – they act as re-configurable logic. FPGAs generally do not store their configuration – it has to be loaded from an external FLASH, EEPROM, or connected processor. CPLDs do store their configuration, so they’re ready as soon as they power up. As a general rule, FPGAs contain more configurable logic than CPLDs. This allows for larger designs to be instantiated with FPGAs. Don’t knock CPLDs though. CPLDs have plenty of room for big designs, like generating VGA signals.
[Carl] also is designing with schematic capture in his tutorial. With the schematic capture method, digital logic schematics are drawn just as they would be in Eagle or KiCad. This is generally considered an “old school” method of design capture. A few lines of VHDL or Verilog code can replace some rather complex schematics. [Carl’s] simple designs don’t need that sort of power though. Going the schematic capture route eliminates the need to learn VHDL or Verilog.
[Carl’s] tutorial starts with installing Altera’s Quartus II software. He then takes the student through the “hardware hello world” – blinking an LED. By the time the tutorial is done, the user will learn how to create a 4 bit adder and a 4 bit subtractor. With all that under your belt, you’re ready to jump into big designs – like building a retrocomputer.
[Image via Wikimedia Commons]
Designing a computer from scratch is one of the holy grails of hardware design. For programmable logic, designing your own processor is a huge accomplishment. That’s exactly what [zhemao] has done. He created EZ8, an 8 bit processor is written in Verilog. EZ8 has a 3 stage pipeline, which makes design very interesting. Instruction set pipelines have been used in processors for many years. They speed up operation by allowing the processor to execute more than one instruction in parallel. The idea is similar to washing, drying and folding laundry. Most people pipeline their laundry. One load is in the washer, another in the dryer, and a third is being folded. Pipelines aren’t a free lunch though – there are hazards. If one instruction requires the result of an instruction which is still being executed in parallel, there’s a problem. In our laundry analogy this would be like having one sock on the folding table while its mate is still in the dryer. The folding operation must wait for the drying operation to complete before the socks can be paired. This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.
[zhemao] didn’t just give us a processor and no support though. He also included an assembler written in OCaml, and an emulator written in C. Several test assembly programs are also up on [zhemao’s] github repo to verify operation. [zhemao] has tested his processor with Altera Cyclone 5 series FPGAs, but it should be possible to port it to other FPGA manufacturers. If you want more information, [zhemao] also has a discussion going on in the ECE subreddit.
[Thanks for the tip LongHornEngineer!]
[Image courtesy of intel]
Flip-flops are extremely simple electronic circuits, forming the basis of clock circuits, memory circuits, buffers, and shift registers. Through his dilly-dallying with digital logic, [Jeffrey] decided he would build his own. Not with Verilog or VHDL, though, but Migen: the Python-based way to build digital circuits with software.
Migen is an interesting tool that makes traditional FPGA programming a lot easier; instead of Verilog or VHDL, Migen allows an FPGA to be programmed in Python. Yes, it’s the tool you’ve been waiting for, and the tutorials make it look pretty easy. After installing Migen, [Jeff] wrote a class for a D flip-flop in only three lines of code. That’s three readable lines of code, and he was able to simulate the flip-flop with gtkwave in another two lines. Compared to learning the complexities of VHDL or Verilog, Migen makes digital logic and FPGA programming a breeze.
[Jeff] has a great tutorial for building a D flip-flop with Migen, but we’d love to see some more complex examples of what can be done with this very cool tool. If you’re building (or have built) something with Migen, be sure to send it in and relate your experiences.
For [Eric]’s entry for our Fubarino Contest, he went down to very low-level hardware and created Pong on an FPGA.
[Eric] used a Basys 2 FPGA board to create this virtual, logic gate version of Pong. Output is via the VGA port, multiplayer and an AI player is implemented, and all the required mechanics for Pong – collision detection, button and switch input, and score keeping are also in this project.
The Fubarino contest requires an easter egg, of course, so when the score for the left player reaches 13 and the score for the right player reaches 37 (get it? 1337?), the previously square ball turns into an extremely pixeley version of the Hackaday logo. The Hackaday URL is also displayed, thanks to [Eric]’s FP(V)GA module for displaying text on his FPGA board.
The improved Pong ball and URL only appears when the scores are 13-37, making this an extremely well-hidden easter egg. Video of [Eric] demoing his Pong below.
This is an entry in the Fubarino Contest for a chance at one of the 20 Fubarino SD boards which Microchip has put up as prizes!
Continue reading “Fubarino Contest: FPGA Pong”
[Brad Robinson] was feeling a bit nostalgic for his Microbee, so he rebuilt it in an FPGA. Not once, but three times. For the uninitiated, the Applied Technology Microbee was a Z80 based computer 1980’s. Designed in Australia, the Microbee did not see much popularity outside its home continent. Even so, the introduction to home computers many Australians was on a Microbee. [Brad] actually wrote several programs for the Microbee, including some games sold by Applied Technology themselves.
Fast forward to 2012, [Brad] is learning FPGAs, and wants to build a Microbee in VHDL. The FPGAbee was born. The first iteration of the FPGAbee began with the CPU, which came from the T80 open source VHDL Z80 core. Around this core [Brad] added the video controller, keyboard, and sound. When he started adding disk functionality, [Brad] ran into some problems. He wanted to use a FAT formatted SD card for cassette and hard disk emulation.
The relative complexities of the FAT format meant he would have to use some custom software to make this work. [Brad] decided to run this software on a second Z80 core. Both cores would need access to memory, and this is where [Brad] learned what he calls “a hard lesson in cross domain clocks” on FPGAs. Multiple clock nets can cause major propagation delay issues. [Brad] was able to work through the problems, but it caused him to step back and re-evaluate the entire design. This was the start of FPGABee2.
Continue reading “Build an FPGA Microbee in Three (Not so) Easy Steps”
[Dave] noted that in a recent poll of FPGA developers, emacs was far and away the most popular VHDL and Verilog editor. There are a few reasons for this – namely, emacs comes with packages for editing your HDL of choice. For those of us not wanting to install (and learn) the emacs operating system, [Dave] got Notepad++ to work with these packages.
Notepad++ already has VHDL and Verilog highlighting along with other advanced text editor features, but [Dave] wanted templates, automated declarations and beautification. To do this, he used the FingerText to store code as snippets and call them up at the wave of a finger.
As [Dave] writes his code, the component declarations constantly need to be updated, and with the help of a Perl script [Dave] can update them with the click of a hotkey. Beautification is a harder nut to crack, as Notepad++ doesn’t even have a VHDL or Verilog beautifier plugin. This was accomplished by installing emacs and running the beautification process as a batch script. Nobody can have it all, but we’re thinking [Dave]’s method of getting away from emacs is pretty neat.
MyHDL is a Python module that brings FPGA programming into the Python environment. [Christopher Felton] tipped us off about a simple tutorial he just finished that gives an overview of how the module is used.
You may remember hearing about PyCPU a couple days ago which can run very simple Python code on a FPGA. There was a healthy discussion in the comments section comparing PyCPU and MyHDL. Although they may seem similar at first, the two are quite different. PyCPU creates a processor on the FPGA chip which can execute a small range of Python code. MyHDL actually implements Hardware Description Language in the Python environment. Once you’re used HDL to model your hardware choices in a Python script, it is converted to VHDL then fed to the toolchain and pushed to the chip like normal.
This is not an absolute beginner’s experience. But if you’re well-versed in Python it makes the jump to HDL a lot easier because you’ll be working with syntax that is already familiar to you.