Reinventing VHDL Badly

May 16, 2016 by Brian Benchoff 21 Comments

A few years ago, Philip Peter started a little pet project. He wanted to build his own processor. This really isn’t out of the ordinary – every few months you’ll find someone with a new project to build a CPU out of relays, logic chips, or bare transistors. Philip is a software developer, though, and while the techniques and theory of building hardware haven’t changed much in decades, software development has made leaps and bounds in just the past few years. He’s on a quest to build a CPU out of discrete components.

Search the Internet for some tips and tricks for schematic capture programs like KiCad and Eagle, and you’ll find some terrible design choices. If you want more than one copy of a very specific circuit on your board, you have to copy and paste. Circuit simulation is completely separate from schematic capture and PCB design, and unit testing – making sure the circuit you designed does what it’s supposed to do – is a completely foreign concept. Schematic capture and EDA suites are decades behind the curve compared to even the most minimal software IDE. That’s where Philip comes in. By his own admission, he reinvented VHDL badly, but he does have a few ideas that are worth listening to.

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Crawl, Walk, Run: Planning Your First CPU Design

March 16, 2016 by Al Williams 42 Comments

I’ve worked with a lot of students who want to program computers. In particular, a lot of them want to program games. However, when they find out that after a few weeks of work they won’t be able to create the next version of Skyrim or Halo, they often get disillusioned and move on to other things. When I was a kid, if you could get a text-based Hi-Lo game running, you were a wizard, but clearly the bar is a lot higher than it used to be. Think of the “Karate Kid”–he had to do “wax on, wax off” before he could get to the cool stuff. Same goes for a lot of technical projects, programming or otherwise.

I talk to a lot of people who are interested in CPU design, and I think there’s quite a bit of the same problem here, as well. Today’s commercial CPUs are huge beasts, with sophisticated memory subsystems, instruction interpreters, and superscalar execution. That’s the Skyrim of CPU design. Maybe you should start with something simpler. Sure, you probably want to start learning Verilog or VHDL with even simpler projects. But the gulf between an FPGA PWM generator and a full-blown CPU is pretty daunting.

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Not Ready For FPGAs? Try A CPLD

December 19, 2015 by Al Williams 24 Comments

[Kodera2t] wanted to experiment with programmable logic. Instead of going with an FPGA board, he decided to build his own CPLD (complex programmable logic device) board, with a built-in programmer. The CPLD is a Xilinx 9536 which is inexpensive and, though obsolete, still readily available. The programmer for the board uses an FT232RL and the total cost is very low ([kodera2t] says it is in the price range of a Raspberry Pi Zero or about $4).

From a user’s point of view, a CPLD is just a small FPGA. Internally, there is a significant difference in how they implement your design. Although there are differences between different product families, CPLDs usually use a sea of logic gates arranged as an AND/OR chain. By feeding inputs and inverted inputs into the AND gates and then ORing the results, you can build interesting logic circuits. However, modern CPLDs use Verilog or VHDL, so you describe what you want just like with an FPGA and the software figures out how to use the underlying circuits to give you what you want.

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Retrocomputing On A Chip

December 3, 2015 by Martin Malý 10 Comments

New electrical components enable us to reconstruct old wiring more efficiently. Especially, the accessible and cheap FPGA kits which offer the possibility to put together wiring of many old computers as an “on-a-chip” solution.

When I managed to get a hold of an old bubble LED display and a pretty mechanical matrix keyboard, I decided to build a replica of an old single board computer. Logical options seemed to be to build either KIM-1 or Heathkit ET-3400. Replicas of KIM-1 already exist, even for Arduino, so my task would be reduced to connect the keyboard and display. But then I told myself that I would use the fact that my bubble display has 9 positions as an excuse to build the legendary Czechoslovak Single Board Computer PMI-80 which used the same display. My replica is an FPGA, or rather an FPGA emulator of this very computer.

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DisplayPort With An FPGA

September 23, 2015 by Al Williams 30 Comments

One of the challenges with display technology is the huge increase in bandwidth that has occurred since LCD panels took over from Cathode Ray Tubes. Low end laptops have a million pixels, UHD (“4K”) displays
have 8 million and the latest Full Ultra HD (“8k”) displays have over 33 million pixels. Updating all those pixels takes a lot of bandwidth – to update a 4k display at 60 Hz refresh rates takes close to a gigabyte per second. 8 billion bits – that is a lot of bits! That’s why VGA ports and even DVI ports are starting to vanish in favor of standards like HDMI and DisplayPort.

The current release of HDMI is 2.0, and is tightly licensed with NDAs and licensing fees. VESA, who created the DisplayPort standard, states the standard is royalty-free to implement, but since January 2010, all new DisplayPort related standards issued by VESA are no longer available to non-members.

So after receiving a new Digilent Nexys Video FPGA development board, Hackaday regular [Hamster] purchased a UHD monitor, scoured the internet for an old DisplayPort 1.1 standard, and started hacking.

A couple of months and 10,000 lines of VHDL code later what may be the first working Open Source DisplayPort
implementation is available. The design includes a 16-bit scrambler, an 8b/10b encoder, and multichannel support.

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Learn FPGAs In Your Browser

July 21, 2015 by Al Williams 40 Comments

FPGAs aren’t really programmed, they are configured. Most designers use Verilog or VHDL to describe the desired circuit configuration. Developers typically simulate these configurations before committing them to silicon (a good habit, especially if you ever graduate from FPGAs to ASICs where changes are very expensive). That simulation takes a lot of software you have to install and learn, right?

Not necessarily. You can do e-mail, word processing, and PCB layout in your browser. Why not FPGA design? The EDAPlayground website provides two editor views: one for your main “code” and another for the testbench (the simulation driver you use to test your design). You can even open multiple files, if you have a complex design.

Once you’ve entered your Verilog or VHDL (or picked one of many examples) you can run the simulation and see the result right in your browser. No software to install, and–outside of actually learning VHDL or Verilog–not much learning curve.

As [Strauburn], [combinatorylogic], and others commented on our recent post about a VHDL CPU, you can do a lot of learning without ever having your hands on real hardware. The web site gives you access to several different tools (useful if you want to see how your code will behave on different tools) and also many standard verification libraries. There are limited synthesis tools, but honestly, if you want to go to real hardware, you are going to want the vendor tools for the specific FPGA you are using.

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Designing A CPU In VHDL For FPGAs: OMG.

July 20, 2015 by Elliot Williams 68 Comments

If you’ve been thinking about playing around with FPGAs and/or are interested in CPU design, [Domipheus] has started a blog post series that you should check out. Normally we’d wait until the whole series is done to post about it, but it’s looking so good, that we thought we’d share it with you while it’s still in progress. So far, there are five parts.

In Part One, [Domipheus] goes through his rationale and plans for the CPU. If you’re at all interested in following along, this post is a must-read. The summary, though, is that he’s aiming to make a stripped-down 16-bit processor on a Spartan 6+ FPGA with basic arithmetic and control flow, and write an assembler for it.

In Part Two, [Domipheus] goes over the nitty-gritty of getting VHDL code rendered and uploaded to the FPGA, and as an example builds up the CPU’s eight registers. If you’re new to FPGAs, pay special attention to the test bench code at the end of the post. Xilinx’s ISE package makes building a test suite for your FPGA code pretty easy, and given the eventual complexity of the system, it’s a great idea to have tests set up for each stage. Testing will be a recurring theme throughout the rest of the posts.

In Part Three, [Domipheus] works through his choices for the instruction set and starts writes up the instruction set decoder. In Part Four, we get to see an ALU and the jump commands are implemented. Part Five builds up a bare-bones control unit and connects the decoder, ALU, and registers together to do some math and count up.

We can’t wait for further installments. If you’re interested in this sort of thing, and are following [Domipheus]’s progress, be sure to let him know: we gotta keep him working.

Of course, this isn’t the first time anyone’s built a soft-CPU in an FPGA. (The OMG was added mostly to go along with the other TLAs.) Here’s a tiny one, a big one, and a bizarre one.