Everyone knows that the perfect capacitor to decouple the power rails around ICs is a 100 nF ceramic capacitor or equivalent, yet where does this ‘fact’ come from and is it even correct? These are the questions that [Graham] set out to answer once and for all. He starts with an in-depth exploration of the decoupling capacitor (and related) theory. [Graham] then dives into the way that power delivery is affected by the inherent resistance, capacitance, and inductance of traces. This is the problem that decoupling capacitors are supposed to solve.
Effectively, the decoupling capacitor provides a low-impedance path at high frequencies and a high-impedance path at low frequencies. Ideally, a larger value capacitor would be better, but since this is the real world and capacitors have ESL and ESR parameters, we get to look at impedance graphs. This is the part where we can see exactly what decoupling effect everyone’s favorite 100 nano-farad capacitors have, which as it turns out is pretty miserable.
Meanwhile, a 1 µF (ceramic) capacitor will have much better performance, as shown with impedance graphs for MLCC capacitors. As a rule of thumb, a single large decoupling capacitor is better, while two MLCC side-by-side can worsen noise. Naturally, one has to keep in mind that although ‘more capacity is better for decoupling’, there is still such a thing as ‘inrush current’ so don’t go too crazy with putting 1,000 µF decoupling capacitors everywhere.
It would have been interesting for the simulation to include board-level capacitors and typical traces there (50-100 mm). 100 nF locally isn’t that “miserable”, because at the board level there are often larger capacitors, and at lower frequencies those take over.
But I agree that for many boards and package size vs. DC voltage combinations, 1 µF does provide better decoupling than 100 nF. The inrush current problem can be quite severe, especially with older regulators.
Most annoying are chips where manufacturers recommend weird capacitor combinations like 1 nF + 100 nF + 10 µF without rationale. It’s hard to know if they really have a purpose, or if they are just slapping a bunch of caps on it in an effort to make sure it works.
The implication there is that the largest capacitor is electrolytic and the smaller ones are ceramic.
Ceramic capacitors exhibit mechanical resonance and their exact value is subject to voltage etc., so picking one large ceramic cap can sometimes result in weird and unpredictable behavior. Having two or three with different values makes sure one works when the other is misbehaving.
As an engineer designing radio products for a job I have had to do a lot of simulation with regard to supply bypassing. One of the things people seem to miss is that the popular technique of “broadbanding” by paralleling ceramic capacitors of different values can produce quite significant “impedance holes” where the inductance of one capacitor resonates with capacitance of the other. With the milliohm ESR of these capacitors, the resonances can be quite pronounced and can cause significant EMC issues or problems when they land on IF or RF frequencies the product uses. In some cases it can even cause stability problems. If you don’t believe this, put the capacitor models into a popular simulator like LTSpice. You will very quickly see the problem.
So how do you solve this then? Add ferrite beads between different capacitors?
At RF you not only depend on discrete components. You also make use of the capacitance between the power planes. As soon as you start using ferrite beads you open another can of worms.
As a rule of thumb, you don’t need multiple ceramic caps of different sizes. If you need serious decoupling (like, it’s an RF amp or a clock synth or something), it’s not a case of just “stick stuff here,” you really want to design a power delivery filter properly.
A lot of older datasheets which show stuff like “10 uF/0.1 uF” in parallel were assuming you’d use an electrolytic for the larger cap, with a bigger ESR (ohm-scale). In that case the small cap would provide a very strong improvement because of its much lower ESR, with the bulk decoupling cap getting you down to ohm-scale impedance faster.
If you do end up with a resonance problem but still need the bulk cap for some reason (like, stability of a regulator) you just damp its pole by adding a small resistor in series, like half an ohm. Obviously you could just use a cap with a higher ESR, but there might be reasons not to.
It’s a lot harder when you get to IF/RF (say, several hundred MHz) frequencies, though, if you’re dealing with multiple power planes, because at that point the physical board structure starts to matter, and you need more expensive tools than a simple equivalent circuit model.
For some reason I remember that my 1996 copy of TI’s Linear & Interface Circuit Applications recommends a 1uF + 0.1uF capacitor on the output of a negative voltage regulator where the 0.1uF capacitor “improves the transient response.” I assume because the different size capacitors have different frequency responses, combining different sizes of capacitors gets you better filtering over a larger frequency range. The bigger capacitor is better at handling low frequency noise while the smaller capacitor is better at handling high frequency noise.
I learned it as “you could calculate the exact matching capacitance or you could slap down a big and a little and see if it’s good enough .”
and the linked blogpost argues that the MODERN 1uF capacitor outperforms the 100nF one for ALL frequencies.
It is often a price issue. you want the larger capacitance, lowest L (~smallest package) and lowest price. You decide where you land.
The 1 + .1 was addressed waaaay down in the article.
The 1uF of nowadays is far superior to the combo of yesteryear.
And cheaper as a 1 pick and place part.
Yeah but back in the old days you could get four for one inside one big can that doubled as a baseball bat and would eventually destroy everything that was hooked up to it
The 100nF was a practical and economical size of ceramic capacitor at the time digital IC’s took off.
1uF or 10uF ceramics were yet to come into existence.
In their day, they had a self resonance (SRF) that was comfortably above the logic they were decoupling.
As IC’s got faster, the 100nF cap segued from a 1cm disc to an 0603 chip, fortuitously raising it’s SRF.
The need to use multiple capacitors where you need multi decade frequency decoupling remains unchanged, as does good layout.
I’m presently trying to bring a radio “up to spec” – which means 3 orders of magnitude, because the designer believes “one ceramic capacitor will do it ‘cos its surface mount”. Well no, about 10 are going to be needed, of 3 different value, plus inductors.
The author argues that 100nF capacitors are irrelevant for decoupling, because one could use capacitors with higher value and similar low cost in the same footprint. The higher capacitance improves the low frequency impedance, and because of that it surely must be better.
However I’d argue that most time a 100nF is suggested by the manufacturer, it’s because its a simple way to add some local capacitance regardless of proximity to other capacitors on the same power plane. The impedance often isn’t critical at all, and even a 10nF would be plenty for some low power chip without significant low frequency load steps.
He also spends quite some time writing about the high frequency decouppeling required for modern chips. This is totally true, but then again the proposed higher capacitance values mostly improve low frequency response. If you want better high frequency response, choose a smaller package for smaller inductance. He provided some very good rule of thumb values for that: https://chaos.social/@gsuberland/112975046998489674
The downsides he identified are real: Higher inrush current, potentially unstable regulators. For ultra low standby power circuits there’s another downside in the form of leakage currents, which typically scale with capacitance and can become significant when compared to standby current of modern ultra low power MCUs. It’s also bad when the circuit frequently enters sleep modes and has to power cycle the entire rail.
My conclusion is quite simple: Use the correct part for the job. If you expect high frequency dI/dt, use small packages, if you expect high current dI/dt use larger capacitance, if you want to optimize for lower power pick smaller values. For everything else, a 100nF is still fine.
Caution with high value MLCC capacitors used for decoupling PSUs: look at the C-vs-V characteristic. Many will have the rated value at 0V, but only 20% (or even 10%) at their rated voltage.
If the capacitor doesn’t have the C-vs-V graph, choose another manufacturer.
C can also vary significantly with temperature.
C0G capacitors are largely immune to those effects, but are only available in smaller values.
Finally, to minimise inductance, use 0306 capacitors instead of 0603.
EDN magazine had an article in the Apr 12, 2007 issue, starting on page 77, that I cut out and kept on this very thing. Our company was rather late going to SMT, because we had our own machines for thru-hole assembly (so we didn’t have to get assembly done outside) and for our low production volumes, the setup charges for SMT assembly amortized out to a high-enough per-piece cost that there didn’t seem to be any benefit. (Obviously that has changed.) We were doing mostly audio, not fast digital stuff. The context of this article is audio and avoiding distortion caused by chip capacitors’ values decreasing as you get closer to their WVDC rating. The easy takeaway for me, for designing our circuits, was avoid anything with a 5 in it, like Z5U, Y5V, etc., and use X7R almost exclusively. The 5’s began dropping capacitance almost as soon as you leave 0V; but the X7Rs’ curve was flat until you get to 20% of the WVDC rating. Our stuff mostly operated at 12V (because of having to work with legacy stuff we had no control over); so with non-rail-to-rail op amps and amplifier ICs that could swing 10V with a 12V supply, 50V ceramic chip capacitors fit the bill just fine. There are other dielectrics of course; but I mentioned the most common ones used in audio. For digital, the matter of distortion becomes immaterial.
FWIW, I did not read the article linked above. It was in a light-blue-gray font against a white background, which it would have to be some kind of emergency to bother to try to read. I don’t know why web developers think they need to “soften” the writing. It dramatically reduces my reading speed and comprehension, both. To all web developers, I say, “Cut it out!!”
Dark theme for me if the site allows it.
It all depends on the application. If you are designing something like a PC motherboard, then you will definitely not be using “rules of thumb” to design. I think this “investigation” stems from the fact that people like their bullet lists of best practices (or, one law to rule them all). It is important to remember that they are just that…recommendations, and not laws of nature. If you don’t know, or don’t understand the current-profile in your loads and supply lines, no capacitor is going to help you. It is called engineering for a reason…
If you are just one of the guys/girls dabbling around in electronics (i.e. more focused on the goal, than the howto), then 100nF ceramic will work fine 99.9% of the time (time-proven recommendation over multiple decades). If, and when it doesn’t, then start burying your head into the design and try and figure out why, otherwise…100nF is good enough. In the real world, this is what most engineers do.
We used to refer to Henry W. Ott books when we had to design something. I seem to remember he had different values and placement depending on the technology (CMOS, TTL, AS TTL, LS TTL and so on).
He is still around …
https://hott.shielddigitaldesign.com/techtips/decoupling.html
I used to fight with a fellow design engineer at my previous job. He’d just copy reference designs from the datasheet (which wasn’t wrong) but he would also randomly sprinkle 10nF/22nF everywhere near the chips. It infuriated me so much, its like he enjoyed wasting money on barely any decoupling effect
Fun exercise, try calculating how much stray capacitance is generated from the power traces against the ground plane (both, on the same layer and on other layers). It will take a bit of effort but do it. You will be surprised to find that its much higher than you expected
I think the blog post trivializes the concept of decoupling to extreme concentration on the the local capacitor. If the difference between running and not is 1uF and 0.1uF decoupling: overall your design is marginal at best. The idea of sprinkling 0.1uF caps around is a great idea- and it was born from the era where there were not economical low ESR 1uF caps to be had. In general, it still works. To add, if you’re using leaded capacitors, the lead inductance is significant- Howard Johnson’s book uses 14nH in an example calculation as a starting point.
Decoupling is not just the capacitors, it is the entire power supply (delivery) design. Each part has a frequency domain. In an overall sense, starting from the lowest frequency, you have the actual supply, then bulk capacitance, then decoupling, then planes.
For a MCU, decoupling capacitors are mostly for the output ring, not the core. A big dI/dt is always going to come from the outputs driving something- so the takeaway is: know what you are driving, a big enough spike of current on an output can mess with the internals indirectly. (NB: many modern MCUs will have an output drive setting.) Don’t directly drive high reactance circuits with a chip that is not designed for that load.
Industry guru Eric Bogatin addresses the 3-capacitor-values myth in the Altium video at https://www.youtube.com/watch?v=y4REmZlE7Jg, “You must Unlearn what You have Learned,” from 10/30/20, on Altium’s channel. He also addresses the myth of copper pours.
FWIW, I did not read the article linked above. It was in a light-blue-grey font against a white background, which it would have to be some kind of emergency to bother to try to read. I don’t know why web developers think they need to “soften” the writing. It dramatically reduces my reading speed and comprehension, both. To all web developers, I say, “Cut it out!!”
hi, I will read the article, definitely; to help you, in chrome if page print to pdf doesnt work because of bad css (here suboptimal), lets select the important text from end to beginning by mouse (touchpads are hell) and print that selected text and use also scaling to 150% or more, this works almost always well and text even reflows being scaled up as bigger… cheers
Years ago I learnt to use the biggest capacitance in the smallest reasonable package usable in the specific layout. And the layout how to connect the capacitor footprint pads to the power rails/planes gets totally neglected here, but is equally important.
Pick your favorite:
https://www.intel.com/content/dam/docs/us/en/683073/current/rlw1628537163382.jpg
I’ve just about given up on expecting people to understand the difference between a decoupling capacitor and a bypass capacitor. A decoupling capacitor is used to allow an ac signal to be propagated between stages of amplification without the different dc levels causing an issue. A bypass capacitor allows variations in current in an individual stage to bypass having to go all the way back to the power supply, through that, and back via the ground, which would cause unnecessary and undesired variations in the supply voltage, which would also be fed into any other stage connected to the same supply. So the clue to the usage is in the name. A bypass capacitor bypasses the power supply; a decoupling capacitor decouples dc between stages of amplification.
You are talking about a coupling capacitor, not a de-coupling capacitor.
Just to add to the equation, monolithic SMD caps give you another way to get it wrong. We had a batch of devices a few years back that passed QC and got into the wild with an annoying characteristic that caused us to go out and replace every one of them. It seems that monolithic caps have no appreciable give, and when they are firmly soldered down they can harmonically resonate with the PCB at certain frequencies, which are not picked up by most adult males. It wasn’t until complaints from women and children started filtering through the all adult male field techs that it was finally acknowledged. I, myself couldn’t hear it unless I pressed my ear up against the chassis. Manufacturing moved to monolithic caps with folded metal standoffs, which gave it enough flex to attenuate the resonance.
OK, give. What company still has field techs for consumer-facing (’cause children) gear, and does unforced recalls??? At least tell us what field. Health tech, maybe?
What company that’s involved in the installation, repair, and maintenance of communications, environmental controls, utilities, or healthcare, that services homes, schools, religious organizations, or medical facilities doesn’t? A black mark on them if they don’t.
I’m not at liberty to discuss my employer, the device, or the device manufacturer, but suffice it to say that it’s in the energy and environmental controls sector.
Oh, I’ve uncountered this gotcha as well! Got a cheap OLED display module, that was emitting annoying noise. Dabbling with inductor produced no results, but once I’ve removed some ceramic caps and replaced others with tantalum it became silent.
I have had this exact problem also, solved in exactly the same way.
interesting, ya, I read from some datasheet recently also that using modern mlcc smd ceramics in case where larger values (electrolyt) were required combined with small ceramic may be replaceable by single larger ceramic today… it was on tiny board to sqzeeze parts count to minimum; altium video is interesting too, but its fact anytimw I hear “lets unlearn and follow something TOTALLY new” I immediatelly feel some modern progresive totality ideology, aka scientology; so will try and watch this being adopted by majority :-) cheers
One of the “sick-puppy, you’re evil” tricks I was taught in college was how to abuse common-pin cap SIP networks/arrays (such as the Bourns 4609M series) as single component decoupling networks for power and signal. Capacitors in Parallel add like resistors in series. Fun times.
Funny how no one is addressing the quality of the dialectic, which has a direct impact on this frequency curves. Half-ass engineering…
Sorry, ‘dielectric’. My fingers do not interface well with my phone keyboard…