Do you know WHY you’re supposed to use decoupling capacitors?

[Bertho] really enjoyed pawing through the pile of projects submitted to the 7400 logic contest. But one thing kept hitting him with the vast majority of the entries: decoupling capacitors were missing from the circuits. If you’ve worked with microcontrollers or digital logic chips you probably know that you’re supposed to add a small capacitor in between the voltage and ground pins for decoupling purposes. But do you know why? [Bertho] put together a great post that looks that the benefits of using decoupling capacitors in your circuits.

He set up a circuit using a 74HC04 inverter and put it to the test. The image above shows current measurments with the inverter under load. Images on the right show a decoupled circuit and the ones on the left shows a circuit without that capacitor. You can see that the decoupled circuit has much smoother signals when driven high. But it’s not just the smoothness that counts here. [Bertho] goes on to discuss the problem of slow rise-time caused by a dip in current flowing into a chip’s VCC pin. It can take a long time to get above the threshold where a chip would recognize a digital 1. Throwing a capacitor in there adds a little reservoir of current, just waiting to fill in when the power rail dips. This feeds the chip in times of need, keeping those logic transitions nice and snappy.

Comments

  1. Monty Werthington says:

    Interesting, Now I know why.

  2. Erik Johnson says:

    Count me in as one of those who doesn’t usually do this when things “just work”. But outside of possible costing; why are decoupling caps not built into the chips? Back-feeding?

    • Bill says:

      Trying to build capacitors onto the silicon of the chip is largely impractical. It takes up way too much real estate on the silicon for the needed capacitance to properly decouple.

    • Bertho says:

      It is very expensive to make a capacitor on a silicon chip. You need capacitance sizes that are in the order of 100..1000 times the load capacitance. Making that in silicon is not an option (or your chip is 99.99% capacitor and 0.01% transistors).

      Adding a capacitor inside the housing is also very expensive. You not only need to use many more steps in fabrication, but the thermal stability of so many different materials in a sealed package is prohibitively expensive.

      You can see on some CPUs that the chips are mounted on an intermediary PCB with some or all capacitors mounted to ensure proper function. But adding $1 to a $250 chip is fine, while adding $1 to a $0.05 chip would be very problematic.

    • johngineer says:

      The chip manufacturer doesn’t know what your power supply circuit looks like, what speed you’re running the chip at, or what kind of load you’re driving with the pins, among other things.

      Every circuit is different, with its own properties that need to be accounted for.

      Also, as Bill and Bertho pointed out, it’s not cost-effective to build caps in silicon.

  3. Colecago says:

    @Erik Johnson
    They don’t know what size caps you need. You might want to target certain frequencies heavier than others, you might not be able to allow the delay on startup caused by a large cap, or maybe the inrush is too much if you have many devices all with large decoupling caps.

  4. Nabil says:

    Intersil has what looks to be a good app note on the topic as well
    http://www.intersil.com/data/an/an1325.pdf

  5. lostalaska says:

    Awesome, having just gotten into digital electronics I didn’t understand the reasoning behind the need for the decoupling capacitors, now I understand the logic behind it.

    You guys need some kind of tag similar to “…and now you know” because this kind of stuff is almost always helpful to me and i’d love to just look at all the useful little tips like this that while not a project in itself it does explain certain concepts that might be very new to us noobs just getting our feet wet in electronics.

  6. neomech says:

    Wow, such useful info! bravo!

  7. DanJ says:

    Also look at your linear voltage regulator spec to see if it needs bypass capacitors on either/both inputs and outputs for stability especially if there is lots of inductance in the circuit (e.g. long runs from the power source). I’ve seen one of these little beasties become unstable.

  8. The Timmy says:

    good stuff to know. until a few minutes ago, I would only use one if it was in the schematic. and I’ve noticed, some circuits would start to act up when the part was omitted or pulled.

    question: is there ever a time where you shouldn’t use one? not a time where it wouldn’t make a difference, but any instances where you would want your circuit coupled?

    • Bertho says:

      Power supply decoupling is normally always required. This goes for both digital and analog circuits.

      There are few exceptions in analog circuits, where adding a bypass might be the cause of instability. This is often seen in linear voltage regulators (as DanJ above noticed in the datasheet). Adding the /wrong/ bypass may cause the circuit to oscillate due to changed loop-gain or phase compensation. This can also be the case in sensitive opamp circuits. These cases are generally documented in the datasheets of the specific devices.

  9. the.hacker.x says:

    I have been studying analog circuit design for two years now, and I can remember, a couple months ago, for about one second I actually understood it :)

  10. Many schematics leave out the decoupling caps, assuming that each chip will get one. Also, circuit boards are often designed with distributed capacitance in the form of two PCB adjacent layers being (mostly) ground and supply voltage. Back in the day, you could buy IC sockets with build-in bypass caps. It is typical practice to place a larger electrolytic cap when the supply voltage comes onto the board, which may also be left off the schematic.

    • Bertho says:

      Agreed, many schematics imply the use of bypass capacitors. However, you would want to draw them if you want to use the schematic to generate a PCB with all components.

      Although two adjacent PCB planes (pwr+gnd) are a capacitor, you cannot count on this as being effective decoupling. A 10x10cm PCB (4-layer FR4) with the inner layers at pwr and gnd, separated at 0.5mm, gives you less than 1nF in capacitance (C = 8.854e-12 * 4.5 * 0.1^2 / 5e-4). A standard bypass capacitor is 100nF.

      The two planes are very effective at shielding, but that is a completely different story (and I’ll leave the very-high-frequency talk at home). You still need the bypass capacitors for decoupling.

      • Cal says:

        That’s only half the story.

        At higher frequencies your decoupling caps become inductive, due to their leads. Even the tiny SMT end caps start getting in the way.

        At those frequencies the Vcc+GND layer pairs are needed to have a low inductance path between power and your chips. The caps alone won’t cut it anymore. Their parasitic inductance would prevent the current to reach the decoupled chips in time, so to speak.

        Luckily this is not a big issue yet at those 16MHz your basic Arduino runs at. At least as long as you don’t have to pass CE conformance…

      • engineersteve says:

        But only 1 sq in of FR-4 (assuming k=4) at 0.003″ plane separation gives you close to 10nF, which is excellent for decoupling higher frequencies (~100MHz). Read up on Altera’s appnotes and they depend on plane capacitance for decoupling large pin count FPGA’s. Using a real capacitor either requires it to be far away from the centrally located power pins or on the opposite side, in which case either the distance, or the via, adds enough parasitic inductance to diminish the effectiveness of the cap.

      • Bertho says:

        @engineersteve
        Indeed spaced at 3mils is different than at 0.5mm (20mils) and measured at different frequency.

        As I noted, the very-high-frequency talk is a different ballgame entirely. The complexity of an AC-analysis on how the system behaves is more than the average hobby-hacker requires.
        Yet another thing is that these very-high-frequency designs generally operate at different (much lower) voltage levels and have a different noise immunity setting. Then there are the implied impedance factors and trace-lengths/symmetry and so forth.
        When you want to build these highly complex designs, you probably have experienced the problems at lower frequencies and are prepared to read the datasheets and app-notes more carefully (and learn the trade from your peers).

  11. NewCommenter1283 says:

    personally i always use extra and maybe extra-extra decoupling caps, both high-quality and large capacity for the best of both worlds (taltanium AND electrlytic) FOR EACH IC unless the IC’s are right next to each other, in which case i use one small taltanium for each IC and a shared electrolytic.

    the ONLY time i had a problem with doing so (extra and extraextra decoupling caps) wasnt digital or even an IC, and involved a long THIN solid wire carrying too much current for it’s size. needless to say there was ringing just like in these o-scope pictures, bcuz the inductance of the LONG wire.

    The lesson: when in doubt; USE EXTRA CAPACITORS!!!

  12. truthspew says:

    Nice to see the full write up. I’ve always had a slightly nebulous understanding of decoupling and now I can actually say I understand it even better.

    I know that capacitor are electrical energy stores. And they will filter out nastiness like ripple, etc.

    And now I have to put together my 125VDC supply circuit. I plan to use an isolation transformer that then feeds a bridge rectifier with some good capacitors to even out the flow.

  13. Peter says:

    Very good article. Based on the meassurments, I’m wondering if you can come up with a standard equation for picking a decoupling cap value. I end up always using 100nF, but that’s based on designs I’ve seen other people use.

    Also a note on the different types and why. Again, I use ceramics because of the low ESR, but would any other types work?

    • Bertho says:

      Nabil (comment above) links to an Intersil app-note that addresses the different types of capacitors (specifically for analog circuits). Generally, a ceramic type with low ESR and low ESL is required (ESR/ESL: Equivalent Series Resistance/Inductance).

      The value is of the bypass capacitor is somewhere between 100..1000 times that of the load capacitance, which often results in a capacitor range from 10nF to 220nF. One of the main considerations is the instantaneous voltage change when energy is stored/retrieved. This change is normally kept within the milliVolt range (as this is translated to pure noise on the power rails).

      All in all, it often shows that a value of 100nF is a good compromise for the different requirements (also think cost/benefit analysis). Therefore, a 100nF one is a cheap capacitor to buy; everybody wants the same one.

      • Pat says:

        Probably the one thing in that app note that is most commonly screwed up is the “multiple capacitors of different values” section. If you look at Fig. 10, you’ll see that if you put multiple caps of the same package, but different values, it does nothing at all. And yet you see this all the time from people, mainly because most voltage regulators recommend multiple caps, but don’t mention they should be of different sizes.

      • engineersteve says:

        @Pat

        To clarify, different values of the same package do not necessarily negate. Large package size introduces inductance which limits high frequency decoupling, so small valued caps in an 0805 don’t work so well. If all the caps were 0402, you wouldn’t have a problem.

        To properly decouple a wideband which includes high frequencies, you must determine the impedance over frequency of each component. Some vendor’s provide this data via component simulator tools (AVX, Johanson, Taiyo Yuden, Murata) but the data can’t always be trusted. The components can be measured individually on a network analyzer. With this data construct an RLC model of each component, and simulate them connected together in SPICE. You should also find a way to model distributed capacitance from planes, trace inductance, via inductance, and your voltage regulator.

        Or just put down a bunch of footprint and swap parts until it works…

  14. gcat122 says:

    Along with improving stability, consistancy, speed of operation, and reducing audible noise(in some circuits) the nearby cap supplies the current pulses that logic ICs draw and thereby reduces the radiated(RF) noise from spikes of current that would travel across long wires back to the supply. Every trace is an antenna that loves to cause problems for every radio receiver nearby. Enough logic noise can bury your signal in self generated garbage.

  15. knuckles904 says:

    To keep things from coupling, duh. Any good geek knows couples are against the natural order

  16. Duffsta says:

    Takes me back! i remember when LS and ALS were waaay to expensive for my uni project, so was stuck with old skool 74xx. i learnt qk about decoupling and that was in sub 10MHz speeds. the cost would have been offset a bit with the PSU not sucking the line voltage down lol ahh low power digital. a qtr century of development!

  17. Just to add to what has already been stated. The reason they are not built into silicone already is because of need for flexibility in design. There is no way to anticipate every circuit combination possible. So after a design is done you have to go through and tune the power supply.

    Secondary function of those caps is to reduce EMI. Now those are usually added to any data lines leaving your circuit. For example ethernet or USB. For home hobbyist it’s not as much of an issue but if you have any intention of passing FCC and/or UL you will have to make sure your circuit is not screaming noise around it to other devices.

    Thirdly. It’s not enough to simply stick a cap on a power trace. The location is actually critical.

  18. Miroslav says:

    Not on rain on everyone’s parade – but I have a serious question:

    If decoupling is such a big deal, why are + and – pins on most ICs widely separated? That makes it a pain to place a cap where it is needed the most – between + and – pins.

    Brief look at a datasheet confirms this: 7400 has gnd on pin 7 and Vcc on 14 – diametrally opposite. LM 324 op amp – pins 4 and 11, on opposite chip sides. Why?

    • johngineer says:

      I’ve often wondered this myself, as it certainly is a little counter-intuitive, but it’s not really a dealbreaker either.

      Use of ground and power planes is very helpful in this regard, as the planes themselves act as a (small) capacitor. Taken over the length and breadth of a typical PCB, the distances sort of average out anyway. In my experience, for most TTL and uController circuits running at <16Mhz, the spacing isn't big enough to create significant inductance in the traces, or set up a parasitic tank circuit.

    • Matt Bennett says:

      To answer the question: why are the power pins separated? Legacy mostly, 74xx series parts were designed when frequencies were much lower and it was easier to design with power rails far apart. Analog and other relatively low frequency linear ICs (like the LM324) are a different beast and are much more tolerant of poor decoupling.
      If you look at most digital ICs from the last 20 or so years that are not obligated to be the same as something that is 40 years old, you will find that their power pins are usually located quite close, and the larger pin count parts will have more than just a single pair of power pins.

      • Miroslav says:

        Thanks John and Matt. So it seems that original 7400 designers were like us, build it first and fix problems latter :) To err is human.

        Since we still have to use old tech, it would be nice to see how far those caps can be from 7400 before problems are encountered. I guess it varies with frequency as well.

      • johngineer says:

        “like us, build it first and fix problems latter”

        speak for yourself :)

        but seriously, i think anticipating problems before they happen (and preventing them) is one of the most rewarding things about engineering. even more fun when you’re efforts don’t work and you have to come up with another solution afterwards :)

  19. Duffsta says:

    ^^ Just to add 2c. decoupling IIRC had a primary role of removing spurious transients on the vcc and gnd. this had the effect of causing state changes as the headroom on TTL ( not CMOS based ) was very small as was the fanout, some thing else that had to be considered. just a note that 74hc(t)xx are CMOS based and have completely different propeties to 74xx 74LSxx 74ALSxx and 74Fxx just have a ‘lil look at the basic specs and try wirewrap proto. you MUST know your design rule back then. HC is so much easier. i’m quite shocked to see that plug-n-play digital goes on ~old man moan ~ sigh ;-)

    • Bertho says:

      The problem is not which family of chips you have, but an intrinsic property of digital logic signals.
      All digital logic signals have an extremely high dU/dt at the transitions; they switch outputs between 0V and 5V in mere nano-seconds. Any, really any, capacitance at the outputs is in your way. Remember: I = C * dU/dt. That implies high currents for fast transitions and that energy has to come from somewhere. With induction in the wiring, you need the bypass capacitor.

      BTW, some of the old 74 series also exhibit a problem of output totem-pole short-circuit at the transitions, which makes the problem worse. Modern chips are matched better, but still need to support the transitions.

      • duffsta says:

        @bertho i agree. my point was that before HC family the noise margin was much lower and transient spikes were more in your mind during the design phase. as were inter-track inductance causing similar effect. with HC much of this knowledge has been lost, but still relevent w\ the greater speeds

  20. scienceguy8 says:

    I learned this the hard way not too long ago. I’ve been doing some contract work for a Canadian company developing air quality monitoring equipment. I designed a printed circuit board for a circuit they developed and omitted a decoupling capacitor they had placed next to a temperature sensor. My reasoning was that you only had to decouple logic ICs, not sensors. Boy, was I wrong. They contacted me this week to design a breakout board for the temperature sensor with a built-in decoupling cap after they noticed really bizarre temperature readings in their prototypes. I’m not making that mistake again.

  21. Duffsta says:

    one book that helped me was “the art of electronics” by horowitz and hill. my dad gave me it back in ’83 when i was 15. cost £25 (1\4 months wages) still have it and i thank my dad for the heads ups.

  22. kuhltwo says:

    Great article!!

  23. Pat says:

    That’s what I said: multiple caps with different values, but the same package – so the same equivalent inductance. Which means they’ll behave exactly the same at high frequencies if they’re the same type (Figure 10 in the Intersil note – the combined parallel impedance is identical to the largest cap’s impedance).

    So to decouple across a large range of frequencies you could use, say, a 100 uF cap in a 1206 package and a 10 uF cap in an 0603 package. But putting a 100 uF cap in a 1206 package and a 10 uF cap in a 1206 package is mostly pointless unless the caps are different types (and then you *still* should’ve gone to a smaller package anyway, most likely).

  24. Willyshop says:

    “[Bertho] put together a great post that looks that…”
    anyone else catch that?

  25. Pete S says:

    I have always put 100n capacitors in my designs but I haven’t used much power planes and ground planes on the PCBs. Should I do that? Should they be solid or “hatched”? Perhaps someone has a good book to recommend on how to properly do layout?

    • The Timmy says:

      I second that request. Would love to know how to properly lay out a board… right now I just put parts where ever the board looks the most tidy, and requires the shortest lengths of wire, and usually try not to run traces or wires under ICs (I’ve been told that’s bad), and try to keep all the parts going the same way (even the non-polar ones)..

    • Bertho says:

      A good power trace design is for most applications sufficient. Putting in copper-fill or pwr/gnd planes without thought may work opposite your intentions.

      If you have a very low-frequency design, then it mostly doesn’t hurt and your PCB manufacturer, depending on their technology, is often happy (because they have to remove less copper). The important thing to consider is the possibility of ground-loops.

      As frequency of the system increases, you must also analyze the copper layout and see how it radiates RF or will impact performance. You add extra capacitance on your signal traces, which under circumstance may impact performance negatively.

      Whether solid or hatched is a good question. A hatch patterns is used for shielding purposes and is generally a bad design for a current carrying power plane (you’ll create many small loops which will radiate RF).

      I don’t know a good book, but most information is available in application notes from chip vendors. They do provide a lot of information what to consider so your design will work as intended.

    • Matt Bennett says:

      Honestly, good layout is a job all in itself- there are many factors in laying out a board, from electrical behavior to manufacturability. The text most often referred to as the best reference (at least in the functional aspect) is Howard Johnson’s “High Speed Digital Design,” ISBN 0-13-395724-1. My copy is signed by the author :)

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s