Breadboarding With A 144-core Processor

At the center of that green PCB is a tiny little processor with way too many cores. It’s the GA144 which was taken for a test-drive on a breadboard by [Andrew Back]. We saw a multi-core Kickstarter project last month. This will cost a lot less and get you more than twice the number of cores. But as was mentioned in the comments on that post, the drawback is the programming language. This chip’s IDE uses Forth.

There is a dev board available, but [Andrew] went instead with a QFN-to-Through-Hole adapter board which he hand soldered. Once he has access to the pins the chip can be programmed with an FTDI adapter which is compatible with the 1.8V logic levels. The provided Forth IDE (arrayForth) is a Windows only program but it does run under Wine. We followed the project through to see him twiddling I/O pins. But we still have trouble thinking of applications for it. In a world of complex and inexpensive FPGA chips, what would you use this type of processor for?

36 thoughts on “Breadboarding With A 144-core Processor

      1. I would use it to blink 144 arrays of LEDs. Also Imagine the Multiplexing you could do , that is 5184 LEDs with a basic multiplexed setup. also for a reasonable application how about robotics, Small unmanned SPACEcraft/Aircraft, Huge Sensor array ( tricorders are out of date now we use onefourtyfourCOREders)

  1. Not just IDE, the language, c was never thought from ground up as parallel tasking/threaded , so we tend to thing as parallel threads instead of multi cores solving a single problem.

    Take the classic example:
    For (i=0; i<99; i )
    A[i] = B[i];

    multi cores cores could run that loop so much faster! But its not native to the c language

    1. technically true, but it is marginally trivial to make that loop be able to split across x many cores using threads.

      To be honest it is quite trivial to make most things parallel in c, just need to program using methods which enable that type of programming…

      The standard engineer (mechy, civil, aero, hell even computer and to a point CS) doesn’t learn to use methods and protocols that easily enable distributed computation. This is the real problem, the ones that NEED to do it will eventually try to do so but with crap code unless they really take the time to learn how to do it properly.

      things like 0mq and pthread help greatly.

      1. I’m currently taking an elective for an electronics eng degree involving distributed computing. Have an exam on pthreads and cuda implementations tomorrow.

        It should be noted a core subject (at most, if not all, Australian unis) teaches a basic implementation of openmp also…

      1. @ewertz said, “Multiple cores don’t help memory or I/O bound workloads a bit.”

        Not true… Often multi-core architectures provide a stack of dedicated memory and a memory channel for each core – that can speed things up quite a bit. Look at the Parallax Propeller Chip data-sheet for a simple example.

      2. Yeah but if each core is clearing it’s own cache — other cores aren’t going to be involved in that — each core can *only* work on it’s own local cache, that data still has to be flushed back to memory (and that will likely happen with DMA) — so again, the original point is still valid — it’s not something you can/should distribute across multiple cores.

        If they were working in the same memory space, then you would, again, need some sort of gate keeper — the problem is even more pronounced on slower I/O, such as non-SSD hard drives, for example.

  2. What would it take to use this as an auxiliary processor for a computer? I imagine sending it a workload via usb and reading the output some time later. You’d be limited by the usb bitrate when sending instructions, but if you have relatively small-size, computationally intensive operations it could be a big deal. An array of these would be incredible

    Anyone know its memory requirements/protocol?

    1. It wouldn’t be of much use as a coprocessor for a pc over USB, due to latency, data rate limitations, etc. An array would create additional issues unless you had a seperate USB bus for each node. The same reason why USB video cards are impractical. If you really want to play with a high core count coprocessor for your PC, use your GPU.

    1. That chip is only 18 ARM cores. The board which is still in development would have 48 chips (864 cores). The computer they want to build with all those cores is not presently in development.

  3. crack a passworded zip file in minutes instead of days or weeks

    PS: put 144 of those 144-core chips, and you get 20736 cores XD

    whats the clock-frequency?

    electrical power draw?

      1. According to the data sheet a test at 1.8V and 22C indicated between 20 million and 100 million instructions per second, depending on mix of instructions being run. Further, at 1.5V it slows to about 2/3 that speed. But for something that can then run on one alkali battery, not bad.

        So this should have, at 1.8V, about the same computational (not I/O or storage) ability of a gross of Arduino’s.

    1. Sadly the ga144, with it’s 18 bit datawidth and it’s 180nm process would perform badly for bitcoin mining.
      The upcoming F32 cores with a decent production technique could do very well.

  4. This isn’t a multicore processor, this is a multicomputer processor. Every computer has its own program space and ram, this is a pretty important distinction as it means every computer can boot up and run it’s own program. Multicore all chips share same memory and program space generally.

    This chip could replace a lot of what FPGA’s are used for as each computer is significantly more powerful than a logic block. Be very good for signal processing, I believe one of the uses is in signal processing inside a hearing aid as need fair amount of processing power and extremely low power draw.

    1. actually no it is about on par with similary priced fpgas in terms of theoretical computational capability.

      It’s advantage are 5 integrated codecs (which are unprecedented afik) and a different approach on programming.

  5. The Arrayforth IDE can be dowloaded for free fromm greenarrays. It has a simulator that is amazing.

    To see it in action, run the ide; type ‘so’, then ‘space bar’, and then ‘d’.

    1. Sorry for spamming. You can download an IDE sounds so cool and sexy but the reality is somewhat different.

      I mean, I was quite interested about this chip when I first saw it. Then I realized that I have just bare chip or expensive board option.

      Now when it appears that there is considerably simple and inexpensive option available, I looked more deeply into it and realized that to program it you have to relay on some text mode IDE from 90s (I actually loved Turbo Pascal and C++ environments but this does not look to get any close to that).

      Perhaps open sourcing this part of the system and letting go the pride could help the situation till there is a time.

      Again, sorry for spamming.

      1. Hye,
        I look very closely to this chip, and Chuck is building a layer to make routes of instructions and/or datas inside the chip.
        This layer’s name is “EtherForth”.
        Just google “Etherforth” and you will see.
        Best regards,

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