Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

Soft cores for FPGAs come in many different flavors, covering a wide range of applications. The Bit-Serial CPU (bcpu) soft core presented by [Richard James Howe] is interesting for taking up just about the most minimal amount of resources (23 slices, 76 LUTs) while providing the means to run a Forth-based (eForth dialect) interpreter. To this CPU core a UART can be added (92 LUTs), as well as other peripherals.

As [Richard] states, the entire core with UART fits in 73 slices (220 LUTs) on a Spartan 6, while requiring a single port BRAM (block RAM). It features a 16-bit accumulator and lacks features such as interrupts, byte addressability and function calls, but those are not required to run the eForth interpreter. The main purpose of this soft core (other than the challenge) is to have a UART-programmable core that can be slotted in any FPGA design. For more serious requirements [Richard] also has the H2 SoC, which can run full-fat FORTH.

Being a bit-serial CPU, the bcpu is of course not particularly speedy, but that is the trade-off when going for maximum space savings. As noted in the project README’s ‘Use cases’, there are two use cases which the author had in mind. The first is as a CPU driving a software-defined, low baud-rate UART, the second as a controller for a VT100 terminal emulator. A VHDL test bench is provided, along with a C-based simulator, which require gforth and GHDL.

Image: Pedant01, CC BY-SA 3.0.

11 thoughts on “Bit-Serial CPU: Ultra-Tiny VHDL-Based CPU With Forth Interpreter

  1. The Spartan-6, now that brings back memories. Something too many missed was the Papillio Pro from the Gadget Factory and the free DesignLab IDE. Was mind blowing to wire up a soft-core, design a circuit, develop the software in the Arduino IDE and do logic analysis all on the chip.

    The AVR soft-core was likely a bit more resource consuming than the Bit-Serial CPU. But maybe some Papillio boards are still around to play with since I would not know where else to get a Spartan 6 board these days.

    1. Yes – I know Jack Gasset from the Gadget Factory. We liaised with James Bowman on getting the J1 Forth computer to run on Papillio boards.

      Jack’s family suddenly grew – so he had to give up the GF and get a full time job.

      1. “Jack’s family suddenly grew – so he had to give up the GF and get a full time job.”

        Do you realise how that reads for people who do not immediately associate the abreviation ‘GF’ with ‘Gadget Factory’? :P :P :P

      1. Years ago someone here on HAD cleared a storage building and gave away a ton of Pano v1 and v2 (I think; some where vga and some dvi). I still have half a box of them sitting around waiting for projects

    1. Wrong.

      The challenge is to boot directly into an app to avoid a 1 buggy 2 malware vulnerable 3 ~unmaintainable update/upgrade infested OS.


      The National Security Agency security requirements given to Sandia National Laboratories in ~1982 demanded that only their app software must be running on a microcontroller hardware/software system.. All other bits must be regarded as potential malware and removed.

  2. That’s… pretty big for a UART. Xilinx provides ultracompact (5 slice each rx/tx) macros with an internal FIFO that only need a 16x bit clock enable which can be virtually free with good baud rate choice.

    The code here is pretty dense so it’s hard to see straight off how hard it would be to integrate. There’s a RISC-V bit-serial CPU (SERV) that I looked at but was too much for what I wanted. Probably will take a look.

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