Another New Old Computer on an FPGA

How would you sell a computer to a potential buyer? Fast? Reliable? Great graphics and sound? In 1956, you might point out that it was somewhat smaller than a desk. After all, in those days what people thought of as computers were giant behemoths. Thanks to modern FPGAs, you can now have a replica of a 1956 computer — the LGP-30 — that is significantly smaller than a desk. The LittleGP-30 is the brainchild of [Jürgen Müller].

The original also weighed about 740 pounds, or a shade under 336 kg, so the FPGA version wins on mass, as well. The LGP-30 owed its relative svelte footprint to the fact that it only used 113 tubes and of those, only 24 tubes were in the CPU. This was possible, because, like many early computers, the CPU worked on one bit at a time. While a modern computer will add a word all at once, this computer — even the FPGA version — add each operand one bit at a time.

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MiSTer Upgrades Vintage Computer Recreations

The MiST project provides an FPGA-based platform for recreating vintage computers. We recently saw an upgraded board — MiSTer — with a similar goal but with increased capability. You can see a video of the board acting like an Apple ][ playing Pac Man, below.

The board isn’t emulating the target computer. Rather, it uses an FPGA to host a hardware implementation of the target. There are cores for Apple, Atari, Commodore, Coleco, Sega, Sinclair and many other computers. There are also many arcade game cores for games like Defender, Galaga, and Frogger.

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Build one, get two: CPLD and STM32 development on a single board

Programmable logic devices have claimed their place in the hobbyist world, with more and more projects showing up that feature either a CPLD or their bigger sibling, the FPGA. That place is rightfully earned — creating your own, custom digital circuitry not only adds flexibility, but opens up a whole new world of opportunities. However, this new realm can be overwhelming and scary at the same time. A great way to ease into this is combining the programmable logic with a general purpose MCU system that you already know and are comfortable with. [Just4Fun] did just that with the CPLD Fun Board, a development board connecting an Arduino compatible STM32F103 Cortex-M3 controller to an Altera MAX II CPLD.

The PCB itself has some standard development board equipment routed to the CPLD: LEDs, buttons, a seven-segment display, and additional GPIO. The rest of the CPLD’s pins are going straight to the STM32 and its SPI, I2C and UART pins. Let’s say you want to create your own SPI device. With the CPLD Fun Board, you can utilize all the pre-existing libraries on the STM32 and fully focus on the programmable logic part. Better yet, every connection from MCU to CPLD has its own pin header connection to attach your favorite measurement device for debugging. And in case you’re wondering — yes, you can attach external hardware to those connectors by setting either MCU or CPLD pins to Hi-Z.

The downside of all this is the need for proprietary design software and a dedicated programmer for the CPLD, which sadly is the everyday reality with programmable logic devices. [Just4Fun] did a great job though writing up a detailed step-by-step tutorial about setting up the environment and getting started with the board, but there are also other tutorials on getting started with CPLDs out there, in case you crave more.

386 Too Much Horsepower? Try a 186, in an FPGA!

Typically when we hear the term “System-on-Chip” bandied around, our mind jumps straight to modern ARM-based processors that drive smartphones and embedded devices around us. Coming a little bit more out of left field is [Jamie]’s 80186 core, that runs on Intel FPGAs.

[Jamie] ran the core through a few vintage PC benchmarks.
[Jamie] has implemented the entire set of 80186 instructions in Verilog, and included some of the undocumented instructions too. This sort of attention to detail is important – real world parts don’t always meet the original specifications on paper, and programmers can come to rely on this. The key to compatibility is understanding how things perform in the real world, not just on the spec sheet.

Not content to simply simulate a CPU, all the necessary peripherals for a complete working system have been worked into the design as well. There’s RAM, a UART, as well as CGA graphics and a PS/2 controller that is necessary if you’d like to actually use any sort of human input device.

[Jamie] has released the code under a GPL licence, and it’s available at GitHub. It’s a good basis if you want to play around with what was once a commercial CPU at a logic level. The development guide is also available if you need to really drill down into the details. It’s a cool project, and makes a great contrast to [Jamie]’s previous work – the Oldland 32-bit core.

 

 

Immersive VR with a 200-Degree Stereoscopic Camera

VR is in vogue, but getting on board requires a steep upfront cost. Hackaday.io user [Colin Pate] felt that $800 was a bit much for even the cheapest commercial 360-degree 3D camera, so he thought: ‘why not make my own for half that price?’

[Pate] knew he’d need a lot of bandwidth and many GPIO ports for the camera array, so he searched out the Altera Cyclone V SOC FPGA and a Terasic DE10-Nano development board to host it. At present, he has four Uctronics OV5642 cameras on his rig, chosen for their extensive documentation and support. The camera mount itself is a 3D-printed octagon so eight of the OC5642 can capture a full 360-degree photo.

Next: producing an image!

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FPGA Metastability Solutions

Gisselquist Technology recently posted a good blog article about metastability and common solutions. If you are trying to learn FPGAs, you’ll want to read it. If you know a lot about FPGAs already, you might still pick up some interesting tidbits in the post.

Don’t let the word metastability scare you. It is just a fancy way of saying that a flip flop can go crazy if the inputs are not stable for a certain amount of time before the clock edge and remain stable for a certain amount of time after the clock edge. These times are the setup and hold times, respectively.

Normally, your design tool will warn you about possible problems if you are using a single clock. However, any time your design generates a signal with one clock and then uses it somewhere with another clock, metastability is a possible problem. Even if you only have one clock, any inputs from the outside world that don’t reference your clock — or, perhaps, any clock at all — introduce the possibility of metastability. Continue reading “FPGA Metastability Solutions”

FPGA Design From Top to Bottom

[Roland Lutz] gave a talk about FPGA design using the free tools for Lattice devices at the MetaRheinMainChaosDays conference this year. You can see the video below. It’s a great introduction to FPGAs that covers both the lowest-level detail and some higher level insight. If you’re getting started with these FPGAs, this video is a must-see.

[Roland] starts with the obligatory introductory material. He then jumps into an actual example before zooming back out to look at the internal details of the Lattice FPGA. For instance, this FPGA supports multiple bitstreams, so you can switch between different “programs” on the fly.

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