Interactive Mandelbrot Set Viewer Runs on FPGAs

The Mandelbrot Set is a mathematical oddity where a simple function creates an infinitely complex landscape that you can literally zoom into forever. Like most people, I’ve downloaded Mandelbrot set viewers and marveled at the infinite whorls and spirals, and then waited while each frame took minutes or hours to render as I zoomed in. [Michael Henning], [Max Rademacher] and [Jonathan Plattner] decided to throw some modern computational muscle at this problem by building an interactive Mandelbrot set viewer using a laptop and two FPGA boards.

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An Amiga 600 With An FPGA Inside

The Amiga is the platform that refuses to die. It must be more than two decades since the debacle surrounding the demise of the original hardware, yet the operating system is still receiving periodic updates, you can still buy Amiga hardware now sporting considerably more powerful silicon than the originals, and its worldwide community is as active as ever.

One of those community projects is the MiSTer FPGA Amiga-on-an-FPGA, and it was this that caught the attention of [Mattsoft]. Impressed with the quality of its recreation of an Amiga, he decided to turn his into a “real” Amiga, so found an Amiga 600 case and keyboard, and set to work. Into the mix went the Terasic DE10-Nano FPGA board, I/O and RAM boards, a Tynemouth Software keyboard interface, a USB hub, and some well-designed 3D-printed parts allow the original Amiga case to be used without modifications.

The Amiga 600 was the base model in the final Amiga range from the early 1990s, and at the time despite its HDD interface and PCMCIA slot it languished in the shadow of its Amiga 1200 sibling. The styling has aged well though, and this upgrade certainly breathes a little life back into the case if not strictly the machine itself. If you want to learn a bit more about MiSTer then a look at the project’s wiki is in order. Perhaps you don’t have an Amiga though and would like to wallow in a bit of nostalgia without splashing out for hardware, in that case, give AROS a look.

Thanks [intric8] for the tip.

Exostiv FPGA Debugging Might be a Bargain

Got $4,000 to spend? Even if you don’t, keep reading — especially if you develop with FPGAs. Exostiv’s FPGA debugging setup costs around $4K although if you are in need of debugging a complex FPGA design and your time has any value, that might not be very expensive. Then again, most of us have a lot of trouble justifying a $4,000 piece of test gear. But we wanted to think about what Exostiv is doing and why we don’t see more of it. Traditionally, debugging FPGAs meant using JTAG and possibly some custom blocks that act like a logic analyzer and chew up real estate on your device. Exostiv also uses some of your device, but instead of building a JTAG-communicating logic analyzer it… well, here’s what their website says:

EXOSTIV IP uses the MGTs (Multi-Gigabit Transceivers) to flow captured data out of the FPGA to an external memory. EXOSTIV IP supports repeating captures of up to 32,768 internal nodes simultaneously at the FPGA’s speed of operation (16 data sets x 2,048 bits).

EXOSTIV IP provides dynamic multiplexer controls to capture even more data sets without the need to recompile. Dynamic ON/OFF controls of data sets let you select the data set and preserve the MGT’s bandwidth for when deeper captures of a reduced set of data is required.

In a nutshell, this means they use high-speed communications to send raw data to a box that has memory and connects back to a PC. That means they can store more data, have more data come out of the chip over a certain time frame, and do sophisticated processing. You can see a video about the device below, and there are more detailed videos on their channel, as well.

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Digitizing Domesday Disks

After the Norman invasion of England, William the Conqueror ordered a great reckoning of all the lands and assets owned. Tax assessors went out into the country, counted sheep and chickens, and compiled everything into one great tome. This was the Domesday Book, an accounting of everything owned in England nearly 1000 years ago. It is a vital source for historians and economists, and one of the most important texts of the Middle Ages.

In the early 1980s, the BBC set upon a new Domesday Project. Over one million people took part in compiling writings on history, geography, and social issues. Maps were cataloged, and census data recorded. All of this was printed on a LaserDisk, meant to be played on an Acorn BBC Master. Now, 30 years on, hardly anyone can read the BBC Domesday Project. Let that be a lesson, kids: follow [Jason Scott] on Twitter.

Even though Acorn computers and SCSI LaserDisks and coprocessors are dying, that doesn’t mean the modern Domesday Disk is lost to the sands of time. This project aims to duplicate the Domesday Disk, and in the process provide a means to archive all LaserDisks. It’s a capture card for LaserDisks, and it also means we can finally make a good rip of the un-specalized Star Wars.

The Domesday Duplicator is a shield that plugs into an Altera DE-0 Nano FPGA board and a Cypress FX3 USB board. The Duplicator itself serves as an analog capture card complete with an RF amplifier and a 40 MSPS ADC — fast enough for any analog video signal. With the 50 Ohm input, it will work with most LaserDisk players, ultimately preserving this incredible historical archive from the early 80s.

Getting Good at FPGAs: Real World Pipelining

Parallelism is your friend when working with FPGAs. In fact, it’s often the biggest benefit of choosing an FPGA. The dragons hiding in programmable logic usually involve timing — chaining together numerous logic gates certainly affects clock timing. Earlier, I looked at how to split up logic to take better advantage of parallelism inside an FPGA. Now I’m going to walk through a practical example by modeling some functions. Using Verilog with some fake delays we can show how it all works. You should follow along with a Verilog simulator, I’m using EDAPlayground which runs in your browser. The code for this entire article is been pre-loaded into the simulator.

If you’re used to C syntax, chances are good you’ll be able to read simple Verilog. If you already use Verilog mostly for synthesis, you may not be familiar with using it to model delays. That’s important here because the delay through gates is what motivates us to break up a lot of gates into a pipeline to start with. You use delays in test benches, but in that context they mostly just cause the simulator to pause a bit before introducing more stimulus. So it makes sense to start with a bit of background on delays.

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FPGA Persistently Rick Rolls You

When [Im-pro] wants a display, he wants it to spin.  So he built a persistence of vision (POV) display capable of showing a 12-bit color image of 131 x 131 pixels at 16 frames per second. You can see a video about the project below, but don’t worry, you can view it on your normal monitor.

The project starts with a Java-based screen capture on a PC. Data goes to the display wirelessly to an ESP8266. However, the actual display drive is done by an FPGA that drives the motor, reads a hall effect index sensor, and lights the LEDs.

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Pipelining Digital Logic in FPGAs

When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a CPU or another complex system is a whole different story. It is like going from “Hello World!” to writing an operating system. There’s a lot to understand before you can make that leap. In this set of articles, I want to talk about a way to organize more complex FPGA designs like CPUs using a technique called pipelining.

These days a complex digital logic system is likely to be on an FPGA. And part of the reason we can get fooled into thinking digital is simple is because of the modern FPGA tools. They hide a lot of complexity from you, which is great until they can’t do what you want and then you are stuck. A good example of that is where you are trying to hit a certain clock frequency. If you aren’t careful, you’ll get a complaint from the tool that you can’t meet timing constraints.

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