FPGA

391 Articles

It’s An Apple Lisa, On A FPGA

May 9, 2026 by 4 Comments

Most of us will know that Apple’s precursor to the Macintosh series of computers was a machine called the Lisa. Something of a behemoth compared to those early Macs, it had a price to match and wasn’t a commercial success. Working Lisas survive, but unlike a Mac you won’t find many at your local swapmeet. But what if you really must try this early Apple GUI? Never fear, because [AlexElectronics] is here with a much more accessible version on a FPGA.

This Lisa has a surprisingly large PCB compared to the size of the FPGA, because of the number of connectors. It takes the approach of mixing new and old in interfaces, for example as well as original Lisa keyboard and mouse support, you can also use modern USB versions. There’s also an HDMI output for a modern monitor, and an SD card. Unexpectedly alongside the FPGA there’s a 40-pin DIP, it’s a UART  chip because there’s no handy pre-built one for that particular chip. We’re told it will be up on GitHub when finalized.

Keeping old computers alive, especially rare ones, is hard. We like projects like this one, and we hope to see more developments. Meanwhile you can see the machine in the video below.

Continue reading “It’s An Apple Lisa, On A FPGA” →

FPGA Powers DIY USB Scope And Signal Generator

April 16, 2026 by 8 Comments

Oscilloscopes and to lesser extent signals generators are useful tools for analyzing, testing and diagnosing circuits but we often take for granted how they work. Luckily, [FromConceptToCircuit] is here to show us how they’re made.

[FromConceptToCircuit] starts by selecting the hardware to use: an Artix-7-based FPGA and an FT2232 USB-serial converter. RS245 in synchronous FIFO mode is selected for its high bandwidth of about 400 Mbps. Then, they show how to wire it all up to your FPGA of choice. Now it’s time for the implementation; they go over how the FT2232 interfaces with the FPGA, going through the Verilog code step-by-step to show how the FPGA makes use of the link, building up from the basic transmission logic all the way up to a simple framed protocol with CRC8-based error detection. With all that, the FPGA can now send captured samples to the PC over USB.

Now it’s PC-side time! [FromConceptToCircuit] first explains the physical pipeline through which the samples reach the PC: FPGA captures, transmits over RS245, FT2232 interfaces that with USB and finally, the software talks with the FT2232 over USB to get the data back out. The software starts by configuring the FT2232 into RS245 mode, sets buffer sizes, the whole deal. With everything set up, [FromConceptToCircuit] explains how to use the FT2232 driver’s API for non-blocking communication.

As a bonus, [FromConceptToCircuit] adds a signal generator feature to the oscilloscope using an I2C DAC chip. They start by explaining what exactly the DAC does and follow up with how it’ll be integrated into the existing system. Then it’s time to explain how to implement the I2C protocol bit-for-bit. Finally combine everything together for one final demo that shows a sine wave on the DAC’s output.

The 3DFX Voodoo Lives Again In An FPGA

March 22, 2026 by 36 Comments

The 3DFX Voodoo was not the first dedicated 3D graphics chipset by any means, but it became the favourite for gamers among the early mass-market GPUs. It would be found on a 3D-processing-only PCI card that sat on the feature connector of your SVGA card. The Voodoo took any game that supported its Glide API into the world of (for the time) smooth and beautiful 3D. They’re worth a bit now, but if you don’t fancy forking out for mid-’90s silicon in 2026, there’s another option. [Francisco Ayala Le Brun] has implemented the 3DFX Voodoo 1 in SpinalHDL for FPGAs.

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Ternary RISC Processor Achieves Non-Binary Computing Via FPGA

March 16, 2026 by 33 Comments

You would be very hard pressed to find any sort of CPU or microcontroller in a commercial product that uses anything but binary to do its work. And yet, other options exist! Ternary computing involves using trits with three states instead of bits with two. It’s not popular, but there is now a design available for a ternary processor that you could potentially get your hands on.

The device in question is called the 5500FP, as outlined in a research paper from [Claudio Lorenzo La Rosa.] Very few ternary processors exist, and little effort has ever been made to fabricate such a device in real silicon. However, [Claudio] explains that it’s entirely possible to implement a ternary logic processor based on RISC principles by using modern FPGA hardware. The impetus to do so is because of the perceived benefits of ternary computing—notably, that with three states, each “trit” can store more information than regular old binary “bits.” Beyond that, the use of a “balanced ternary” system, based on logical values of -1, 0 , and 1, allows storing both negative and positive numbers without a wasted sign bit, and allows numbers to be negated trivially simply by inverting all trits together.

The research paper does a good job of outlining the basis of this method of computing, as well as the mode of operation of the 5500FP processor. For now, it’s a 24-trit device operating at a frequency of 20MHz, but the hope is that in future it would be possible to move to custom silicon to improve performance and capability. The hope is that further development of ternary computing hardware could lead to parts capable of higher information density and lower power consumption, both highly useful in this day and age where improvements to conventional processor designs are ever hard to find.

Head over to the Ternary Computing website if you’re intrigued by the Ways of Three and want to learn more. We perhaps don’t expect ternary computing to take over any time soon, given the Soviets didn’t get far with it in the 1950s. Still, the concept exists and is fun to contemplate if you like the mental challenge. Maybe you can even start a rumor that the next iPhone is using an all-ternary processor and spread it across a few tech blogs before the week is out. Let us know how you get on.

M8SBC-486 Is An FPGA-Based “Kinda PC Compatible” 486 SBC

January 8, 2026 by 25 Comments

[Editor’s note: We got this one wrong! The computer uses an actual 486: the FPGA is running essentially as the chipset, interfacing the RAM and the ISA bus with the CPU. And since this went to press, [maniek-86] put out a nicer writeup of the project, which you should go check out, in addition to the GitHub link below.]

 

Given the technical specs of the FPGAs available to hobbyists these days, it really shouldn’t be a shock that you can implement a relatively-modern chipset on one, like one for a 486 system. In spite of knowing that in the technical sense, we were still caught off guard by [maniek-86]’s M8SBC project that does just that– the proas both CPU and BIOSducing a 486 FPGA chipset with a motherboard to boot.

Boot what? Linux 2.2.6, MS-DOS 6.22 or FreeDOS all work. It can run DOOM, of course, along with Wolfenstien 3D, Prince of Persia, and even the famous Second Reality demo– though that last without sound. [maniek-86]’s implementation is lacking direct memory access, so sound card support is right out. There are a few other bugs that are slowly being squished, too, according to the latest Reddit thread. Continue reading “M8SBC-486 Is An FPGA-Based “Kinda PC Compatible” 486 SBC” →

A photo of the PiStorm68K circuit board

PiStorm68K Offers Supercharged Retro Amiga Experience

January 6, 2026 by 11 Comments

[AmiCube] has announced their new PiStorm68K special edition MiniMig accelerator board. This board was developed to replace the 68000 CPU in a MiniMig — a recreation of the original Amiga chipset in an FPGA allowing a real genuine 68000 CPU to operate.

The PiStorm68K itself can host a real genuine 68000 CPU but it can also host various Raspberry Pi models which can do emulation of a 68000. So if you combine a PiStorm68K with a MiniMig you can, at your option, boot into an emulated environment with massively increased performance, or you can boot into an original environment, with its reliable and charming sluggishness.

In the introduction video below, [AmiCube] uses the SYSINFO utility software to compare the CPU speed when using emulation (1531 MIPS) versus the original (4.47 MIPS), where MIPS means Millions of Instructions Per Second. As you can see the 68000 emulated by the Raspberry Pi is way faster than the original. The Raspberry Pi also emulates a floating-point unit (FPU) which the original doesn’t include and a memory management unit (MMU) which isn’t used.

If you’re interested in old Amiga tech you might also like to read about Chip Swap Fixes A Dead Amiga 600 or The Many-Sprites Interpretation Of Amiga Mechanics.

Continue reading “PiStorm68K Offers Supercharged Retro Amiga Experience” →

PJON, Open Single-Wire Bus Protocol, Goes Verilog

December 13, 2025 by 13 Comments

Did OneWire of DS18B20 sensor fame ever fascinate you in its single-data-line simplicity? If so, then you’ll like PJON (Padded Jittering Operative Network) – a single-wire-compatible protocol for up to 255 devices. One disadvantage is that you need to check up on the bus pretty often, trading hardware complexity for software complexity. Now, this is no longer something for the gate wielders of us to worry about – [Giovanni] tells us that there’s a hardware implementation of PJDL (Padded Jittering Data Link), a PJON-based bus.

This implementation is written in Verilog, and allows you to offload a lot of your low-level PJDL tasks, essentially, giving you a PJDL peripheral for all your inter-processor communication needs. Oh, and as [Giovanni] says, this module has recently been taped out as part of the CROC chip project, an educational SoC project. What’s not to love?

PJON is a fun protocol, soon to be a decade old. We’ve previously covered [Giovanni] use PJON to establish a data link through a pair of LEDs, and it’s nice to see this nifty small-footprint protocol gain that much more of a foothold, now, in our hardware-level projects.

We thank [Giovanni Blu Mitolo] for sharing this with us!