This fractal viewer is a great way to get your feet wet with Field-Programmable Gate Arrays. The project will give you some experience working with video output, user input, and a whole bunch of math and memory management. [Hamster] built it using the Papilio Plus board which hosts a Spartan 6 FPGA. This continues his odyssey into the realm of hardware design; part of which we looked at back in December.
The arcade Megawing for the dev board gives him easy access to the controls needed to scroll and zoom on the fractal design. Calculations to generate the shape are being run at 240 MHz, with the VGA output running at 80 MHz. The device has enough horse power and SRAM to show an 800×600 pixel output with a 60 Hz refresh rate.
We really liked the logic diagram that [Hamster] drew up when planning how the calculations would be handled. It’s not overly complex, but it took us a while to conceptualize how everything fits together. It’s certainly an improvement from his last attempt as we couldn’t make heads or tails out of that flow chart.
If you’re just interested in the pretty shapes and colors there’s a demo embedded after the break.