Flash: Arduino Vidor FPGA Instructions Hit France

If you speak French and you have an Arduino Vidor 4000, you are in luck because there’s some good news. The good news is there’s finally some inside information about how to configure the onboard FPGA yourself. The bad news though is that it is pretty sparse. If your high school French isn’t up to the task, there’s always Google Translate.

We knew some of this already. You’ll need Quartus, the FPGA design tool from Altera — er, Intel — and we know about the sample project on GitHub, too. Instead of using conventional Verilog or VHDL, the new information uses schematic capture, but that’s OK. All the design entry winds up in the same place, so it should be easy to adapt to the language of your choice. In fact, in part 2 they show both some schematics and some Verilog. Google Translate does have a little trouble with code comments, though. If you want something even stouter, there’s an example that uses Verilog to output a video frame.

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Logic Analyzers for FPGAs: A Verilog Odyssey

Sometimes you start something simple and then it just leads to a chain reaction of things. I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects. That led to a small problem: how do you show what’s going on inside? In this series of posts, we’ll look at building a logic analyzer into an FPGA to help debug itself, instantiating memory, and — finally — state machines.

Logic analysis is a common tool in FPGA development. If you use Altera, they have Signal Tap available that lets you build a simple logic analyzer into the FPGA that talks back to your PC. Xilinx has ChipScope which is about the same. Sometimes those tools either cost money or are limited in some way in the free versions. I have my sights set on a tool that can be used with the Lattice architecture.

Sure, you can ship data out on I/O pins and then use a regular logic analyzer to pick up the data. But that isn’t very handy. So I thought about writing a generic logic analyzer component. But before I did I decided to check to see if someone else had already done it.

Spoiler alert: they did, but I wanted something a little different so I wound up extending the program significantly. What I wound up with is a reasonably portable Verilog logic analyzer that can produce traces like this one:

Keep in mind, this isn’t a simulation. This is real data pulled off the actual FPGA. Yes, that is gtkwave producing the plots, but the input data is a VCD file generated from samples taken inside the FPGA.

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Friday Hack Chat: FPGA Bootcamp

For this week’s Hack Chat, we’re going to be talking all about FPGAs, with our own resident FPGA expert.

This summer, Hackaday.io launched FPGA bootcamps, simple, easy-to-follow tutorials that will get you up and running with Verilog. These were all done by Al Williams, Hackaday’s resident FPGA hacker. Al’s an electrical engineer, author of over thirty books, countless magazine articles, and thousands of blog posts. He’s been an amateur radio operator for 41 years, and his first computer used an 1802 chip.

Now Al is putting a little bit of his wisdom over on Hackaday.io. He’s written up a bunch of tutorials that will get you started in programmable digital logic. Everything from a refresher on the ins and outs of nands and nors. a short introduction to Verilog, moving into sequential logic, to putting that code on real FPGA hardware is already up, and this bootcamp isn’t done yet.

If you want to get started in FPGA design, Al’s the guy you want to talk to. During this Hack chat, you’ll be able to ask questions about FPGAs, and about what’s coming up in future bootcamps. We’ll also be talking about Al’s other projects that you might see on Hackaday in the future, like the embedded logic analyzer, his IceStorm workflow, and much more.

During this Hack Chat, we’re going to be talking about:

  • How to use the FPGA tutorials
  • What other FPGAs you can use the tutorials for and how
  • Other Hackaday Bootcamp topics — FPGA or otherwise — that you’d like to see.

You are, of course, encouraged to add your own questions to the discussion. You can do that by leaving a comment on the FPGA Bootcamp Hack Chat and we’ll put that in the queue for the Hack Chat discussion.

join-hack-chat

Our Hack Chats are live community events on the Hackaday.io Hack Chat group messaging. This week we’ll be sitting down on Friday, October 12th, at noon, Pacific time. If time zones got you down, we have a handy time zone converter.

Click that speech bubble to the right, and you’ll be taken directly to the Hack Chat group on Hackaday.io.

You don’t have to wait until Friday; join whenever you want and you can see what the community is talking about.

Programming A RISC-V Softcore With Ada

We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based TinyFPGA-BX FPGA board, which we have covered in the past.

The blog post describes how to use the Community edition of the GNAT Ada compiler to set up the development environment, before implementing a simple example project that controls a strip of WS28212b RGB LED modules. There are two push buttons changing the animation and brightness of the lights.

The source can be found at the author’s Github repository, and contains both the Ada source and the Verilog source for the PicoRV32 softcore. To build the project one needs the GNAT compiler, as well as the open-source iCE40 development tools to compile the softcore.

There is a video demonstrating the finished example project, that we’ve placed below the break.

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Easy FPGA CPU with MAX1000

Ok, we’ll admit it. We like FPGAs because it reminds us of wiring up a 100-in-1 kit when we were kids. But the truth is, many projects are just as well off to have a CPU. But there’s a real sweet spot when you have a CPU and an FPGA together. Intel (or Altera, if you prefer) has the NIOS II CPU core, but that’s hard to configure, right? Maybe not, thanks to a project by [jefflieu] over on GitHub. He’s assembled some basic definitions and libraries to easily — relatively speaking — use NIOS II on the MAX1000 as well as a few other boards. The MAX1000 is a pretty nice board for about $30, so this is a very inexpensive way to get into “System on Chip” (SOC) development.

[jeff] goes into more detail in a blog post, but the idea is pretty simple. We tried it, and it works very well, although we found a few things hard to follow so read on to see how we managed.

The idea behind SoC development is you define your CPU configuration and then your hardware devices. Then you write software to talk to those custom hardware devices and — of course — write your actual application code. So you don’t just write a program, you also define the CPU the program will run on and the hardware that it will talk to.

There are several ready-to-go I/O devices included in the project, but the real fun will be writing your own. The Intel tools have the C compiler and everything else you need. You could also do everything from scratch, but these tools make it much easier to get started.

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iCEstick Makes Terrible Radio Transmitter

We’ve done a lot of posts on how to use the Lattice iCEstick ranging from FPGA tutorials to how to use one as a logic analyzer. If you picked up one of these inexpensive boards here’s a fun little experiment. [T4D10N] saw a project [Hamster] put together to send SOS on the FM radio band using nothing but an FPGA. [Hamster used a Spartan], so he decided to do the same trick using an iCEstick with the open source IceStorm tools.

You might be surprised that the whole thing only takes 53 lines of Verilog — less if you cut out comments and whitespace. That’s because it uses the FPGA’s built-in PLL to generate a fast clock and then uses a phase accumulator divider to produce three frequencies on the FM radio band; one for a carrier and two for a tone, spaced 150 Hz apart. The result is really frequency shift keying but you can hear the results on an FM radio.

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FPGA Jacked Into Pinball Machine Masters High Scores

How do you preserve high scores in an old arcade cabinet when disconnecting the power? Is it possible to inject new high scores into a pinball machine? It was the b-plot of an episode of Seinfield, so it has to be worth doing, leading [matthew venn] down the rabbit hole of FPGAs and memory maps to create new high scores in a pinball machine.

The machine in question for this experiment is Doctor Who from Williams, which, despite being a Doctor Who pinball machine isn’t that great of a machine. Still, daleks. This machine is powered by a Motorola 68B09E running at 2MHz, with 8kB of RAM at address 0x0000. This RAM backed up with a few AA batteries, and luckily is in a DIP socket, allowing [matthew] to fab a board loaded up with an FPGA development board that goes between the CPU and RAM.

The basic technique for intercepting and writing a new high score for this pinball machine comes from the incredible [sprite_tm] who is tweeting high scores from a 1943 cabinet. The idea is simple: just have an FPGA look at one specific memory address, and send some data to a computer when the data at that address is updated. For the Doctor Who pinball machine, this is slightly harder than it sounds: the data isn’t stored in hex, but packed BCD. After a little bit of work, though, [matthew] was able to write new high scores from a Python script running on a laptop. All the code (and a few more details) are over on a Github

Extending arcade games by tapping into address and data lines isn’t something we see a lot of, but it has been done, most famously with the Church of Robotron. Here, a few MAME hacks turn a game of Robotron into a Church for the faithful to fully commit themselves to the savior of the world, due to arrive in 66 years and save the remaining humans from the robot apocalypse. This hack of a Doctor Who pinball machine goes beyond a modded version of MAME, and if we’re ever going to make a real chapel with a real game of Robotron, these are the techniques we’re going to use.