fpga

528 Articles

Tiny Tapeout 4: A PWM Clone Of Covox Speech Thing

June 21, 2024 by 4 Comments

Tiny Tapout is an interesting project, leveraging the power of cloud computing and collaborative purchasing to make the mysterious art of IC design more accessible for hardware hackers. [Yeo Kheng Meng] is one such hacker, and they have produced their very first custom IC for use with their retrocomputing efforts. As they lament, they left it a little late for the shuttle run submission deadline, so they came up with a very simple project with the equivalent behaviour of the Covox Speech Thing, which is just a basic R-2R ladder DAC hanging from a PC parallel port.

The computed gate-level routing of the ASIC layout

The plan was to capture an 8-bit input bus and compare it against a free-running counter. If the input value is larger than the counter, the output goes high; otherwise, it goes low. This produces a PWM waveform representing the input value. Following the digital output with an RC low-pass filter will generate an analogue representation. It’s all very simple stuff. A few details to contend with are specific to Tiny Tapout, such as taking note of the enable and global resets. These are passed down from the chip-level wrapper to indicate when your design has control of the physical IOs and is selected for operation. [Yeo] noticed that the GitHub post-synthesis simulation failed due to not taking note of the reset condition and initialising those pesky flip-flops.

After throwing the design down onto a Mimas A7 Artix 7 FPGA board for a quick test, data sent from a parallel port-connected PC popped out as a PWM waveform as expected, and some test audio could be played. Whilst it may be true that you don’t have to prototype on an FPGA, and some would argue that it’s a lot of extra effort for many cases, without a good quality graphical simulation and robust testbench, you’re practically working blind. And that’s not how working chips get made.

If you want to read into Tiny Tapeout some more, then we’ve a quick guide for that. Or, perhaps hear it direct from the team instead?

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Is That A Large Smartwatch? Or A Tiny Cray?

June 21, 2024 by 6 Comments

While we aren’t typically put off by a large wristwatch, we were taken a bit aback by [Chris Fenton]’s latest timepiece — if you can call it that. It’s actually a 1/25th-scale Cray C90 worn as a wristwatch. The whole thing started with [Chris] trying to build a Cray in Verilog. He started with a Cray-1 but then moved to a Cray X-MP, which is essentially a Cray-1 with two extra address bits. Then he expanded it to 32 bits, which makes it a Cray Y-MP/C90/J90 core. As he puts it, “If you wanted something practical, go read someone else’s blog.”

The watch emulates a Cray C916 and uses a round OLED display on the top. While the move from 22 to 32 address bits sounds outdated, keep in mind the Cray addresses 64-bit words exclusively, so we’re talking access to 32 gigabytes of memory. The hardware consists of an off-the-shelf FPGA board and a Teensy microcontroller to handle mundane tasks like driving the OLED display and booting the main CPU. Interestingly, the actual Cray 1A used Data General computers for a similar task.

Of course, any supercomputer needs a super program, so [Chris] uses the screen to display a full simulation of Jupiter and 63 of its moons. The Cray excels at programs like this because of its vector processing abilities. The whole program is 127 words long and sustains 40 MFLOPs. Of course, that means to read the current time, you need to know where Jupiter’s moons are at all times so you can match it with the display. He did warn us this would not be practical.

While the Cray wouldn’t qualify as a supercomputer today, we love learning about what was state-of-the-art not that long ago. Cray was named, of course, after [Seymour Cray] who had earlier designed the Univac 1103, several iconic CDC computers, and the Cray computers, of course.

Comparing X86 And 68000 In An FPGA

June 7, 2024 by 15 Comments

[Michael Kohn] started programming on the Motorola 68000 architecture and then, for work reasons, moved over to the Intel x86 and was not exactly pleased by the latter chip’s perceived shortcomings. In the ’80s, the 68000 was a very popular chip, powering everything from personal computers to arcade machines, and looking at its architecture and ease of programming, you can see why this was.

Fast-forward a few years, and [Michael] decided to implement both cores in an FPGA to compare real applications, you know, for science. As an extra bonus, he also compares the performance of a minimal RISC-V implementation on the same hardware, taken from an earlier RISC-V project (which you should also check out !)

Utilizing their ‘Java Grinder’ application (also pretty awesome, especially the retro console support), a simple Mandelbrot fractal generator was used as a non-trivial workload to produce binaries for each architecture, and the result was timed. Unsurprisingly, for CISC architectures, the 68000 and x86 code sizes were practically identical and significantly smaller than the equivalent RISC-V. Still, looking at the execution times, the 68000 beat the x86 hands down, with the newer RISC-V speeding along to take pole position. [Michael] admits that these implementations are minimal, with no pipelining, so they could be sped up a little.

Also, it’s not a totally fair race. As you’ll note from the RISC-V implementation, there was a custom RISC-V instruction implemented to perform the Mandelbrot generator’s iterator. This computes the complex operation Z = Z2 + C, which, as fellow fractal nerds will know, is where a Mandelbrot generator spends nearly all the compute time. We suspect that’s the real reason RISC-V came out on top.

If actual hardware is more your cup of tea, you could build a minimal 68k system pretty easily, provided you can find the chips. The current ubiquitous x86 architecture, as odd as it started out, is here to stay for the foreseeable future, so you’d just better get comfortable with it!

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What’s The Difference Between Tang 9K And 20K (It Isn’t 11…)

June 6, 2024 by 18 Comments

[Grug Huhler] has been working with the Tang Nano 9K FPGA board. They are inexpensive, and he noticed there is a 20K version, so he picked one up. Of course, you’d expect the 20K board has a different FPGA with more gates than the 9K, but there are also a number of differences in the host board. [Grug] was kind enough to document the differences in the video below.

In addition to the differences, there’s a good demo of the boards hosting a system-on-chip design. The little DIP package is handy for breadboarding. All of the 20K pins are 3.3 V, according to the documentation. The 9K does have some 1.8 V pins. There are more external devices on the 20K board but that eats up more uncommitted pins. Depending on your design, that may or may not be a problem.

We keep meaning to pick some of these up to play with. The Verilog is easy enough, and the tools look adequate. If you need a refresher on Verilog, we have a boot camp for you that would probably port easily enough to the Tang system. We’ve been following [Grug’s] work on these chips lately, and you should, too.

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Use That One Port For High-Speed FPGA Data Export

June 1, 2024 by 7 Comments

There’s a good few options for exporting data out of FPGAs, like Ethernet, USB2, or USB3. Many FPGAs have a HDMI (or rather, sparkling DVI) port as well, and [Steve Markgraf] brings us the hsdaoh project — High-Speed Data Acquisition Over HDMI, using USB3 capture cards based on the Macrosilicon MS2130 chipset to get the data from the FPGA right to your PC.

Current FPGA-side implementation is designed for Sipeed Tang chips and the GOWIN toolchain, but it should be portable to an open-source toolchain in the future. Make sure you’re using a USB3 capture card with a MS2130 chipset, load the test code into your FPGA, run the userspace capture side, and you’re ready to add this interface to your FPGA project! It’s well worth it, too – during testing, [Steve] has got data transfer speeds up to 180 MB/s, without the USB3 complexity.

As a test, [Steve] shows us an RX-only SDR project using this interface, with respectable amounts of bandwidth. The presentation goes a fair bit into the low-level details of the protocol, from HDMI fundamentals, to manipulating the MS2130 registers in a way that disables all video conversion; do watch the recording, or at least skim the slides! Oh, and if you don’t own a capture card yet, you really should, as it makes for a wonderful Raspberry Pi hacking companion in times of need.

The 6809 Lives On In An FPGA

May 28, 2024 by 35 Comments

At one point, the Motorola 6809 seemed like a great CPU. At the time it was a modern 8-bit CPU and was capable of hosting position-independent code and re-entrant code. Sure, it was pricey back in 1981 (about four times the price of a Z80), but it did boast many features. However, the price probably prevented it from being in more computers. There were a handful, including the Radio Shack Color Computer, but for the most part, the cheaper Z80 and the even cheaper 6502 ruled the roost. Thanks to the [turbo9team], however, you can now host one of these CPUs — maybe even a better version — in an FPGA using Verilog.

The CPU may be old-fashioned on the outside, but inside, it is a pipeline architecture with a standard Wishbone bus to incorporate other cores to add peripherals. The GitHub page explains that while the 6809 is technically CISC, it’s so simple that it’s possible to translate to a RISC-like architecture internally. There are also a few enhanced instructions not present on the 6809.

In addition to the source code, you’ll find a thesis and some presentations about the CPU in the repository. While the 6809 might not be the most modern choice, it has the advantage of having plenty of development tools available and is easy enough to learn. Code for the 6800 should run on it, too.

Even using through-hole parts, you can make a 6809 computer fit in a tiny space.You can also break out a breadboard.

Peering Inside The Tang FPGA

May 6, 2024 by 14 Comments

[Grug] has been working with the Tang Nano 9K FPGA board. He wanted to use the Gowin Analysis Oscilloscope (GAO) to build an internal monitor into the device for probing internal points. The problem is that the documentation is a bit lacking, so he made a video showing how to make it work to help us all out.

The idea for this isn’t unique, although for some vendors, getting this capability requires you to buy a license or the free versions are limited. We were disappointed, as was [Greg], that he had to run Windows to get the software to work.

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