ARM Unveils New, High Efficency CPU

ARM has announced their latest IP core the Cortex A32. This 32-bit chip brings the benefits of the ARMv8-A architecture to low-power devices, ostensibly ones that will be the backbone of the Internet of Things.

For the last few years, the state of ARM CPUs has been firmly planted in the world of ARMv7 instructions. These chips, the Cortex A5, A7, A9, A15, and A17 are divided into ‘good, better, best’ segments, with the A7 pulling its weight as the processor in the Raspberry Pi 2, and a dual-core A15 finding its way into the latest BeagleBoard. While these CPUs are very capable, they don’t support the latest ARM architecture, ARMv8. For the last few years, the only ARM processors with the v8 architecture fell into the ‘better’ and ‘best’ segments. Although the A53, A57, and A72 chips are very capable, there hasn’t been a low power ARMv8 chip until this announcement.

So what does this announcement mean for the next generation of the Internet of Things, single board computers, and the wearable electronics of tomorrow? Absolutely nothing. Only the processor IP was released, and it will take at least a year for this core to make it into a chip. It will be 18 to 24 months until you can find this core in a consumer device. On the other hand, when these devices do appear, they will be significantly faster than current devices with a Cortex A5 and A7.

40 thoughts on “ARM Unveils New, High Efficency CPU

  1. The Arduino Due is a microcontroller board based on the Atmel SAM3X8E ARM Cortex-M3 CPU. And it feels like almost nobody uses it. Plus, it isn’t exactly economical either. Or 5V tolerant.

    The Arduino Tre is a Sitara AM335x ARM Cortex-A8 base but it’s been “coming soon” since, uhh, 2013.

    Excited to see this being used in a low power, capable, low cost board. Arduino Quattro?

    1. Nobody uses it because the chip is huge and complex and expensive. But with the recent release of the Zero, a bunch of small Arduino-compatible ARM boards has cropped up including my own Neutrino, and soon Tau.

      And while they may not be 5V tolerant, 5V operation isn’t everything. Want to interface with a MicroSD card and OLED display, as with another board of mine, the Pixel? If you do that with a chip running on 5V you’ll need a couple level shifters because they want to operate at 3V. Granted you can’t drive all LEDs at 3V, and you still need 5V for driving servos, but most sensors and things out there either require or work fine with 3V logic.

        1. +1,000,000 for the Teensy series! Amazing little beasts. :) Very powerful, low power, on-board DAC (3.x series), capacitive-touch.. along with all the toys you might find in an Arduino. And the recent 16bit sound board for $11 is absolutely stunning!

      1. So far TI has only released pre-production silicon and while the idea of mating MSP430 peripherals to the ARM architecture is a good idea in theory TI botched the implementation in many ways.

  2. “What is it good for?”
    Absolutely Nothing!

    Why waste money on a low power IP core when you can use older IP for less? The wireless system is the main power consumer anyway.
    The key thing this 64 – minus – 32 core has is the encryption instructions, and that’s unlikely to be beneficial for hackers.

  3. Just to be clear, here all Cortex-A CPUs are meant to be used with an MMU and an operating system such as Linux. The cortex-M CPUs are meant for microcontrollers running an RTOS or bare-metal code.

    It seems that ARM has been finding it challenging to develop power efficient 64-bit cores. The Cortex A72 while being more performant than even the cortex A15 (most performant 32-bit ARM core), it is not nearly as power efficient. This is why this A32 version is being released.

    1. You are right that the Cortex-A CPU are ideal target for operating system like Linux. While making efficient 64-bit cores is challenging, 32-bits Linux kernel face a real problem for systems designed today to potentially run as long as in 2038 where the 32-bits time_t will overflow. Actually the number of such systems is very low, but as the time pass it will increase exponentially. More information here: https://lwn.net/Articles/643234/

  4. I’m more familiar with the cortex-M series, which I consider enhanced 8-bit machines.
    After all, each memory address can only hold 8 bits. You can’t keep a 32-bit instruction (or even a 16-bit one) in a single address.
    This plays havoc with the values you can store in the PC (r15).
    I hope the A series cores are better.

    1. Do you think that being the memory 8 bit addressable is a disadvantage? Maybe you don’t know that how the memory is addressable is independent of how wide the memory data bus is. About putting random values in the program counter, I don’t really know what do you pretend to do, as you need to know the exact address of an instruction whatever the address width is. You also probably think (wrongly) that if the memory would be 32 bit addressable, a valid instruction would start at every address.

      1. I will stand by the claim: if the memory was 16 bits wide, Thumb instructions would be one (or two) addresses long, effectively doubling the number of instructions that could be addressed. If memory is 32 bits wide AND you use conventional 32-bit instructions, you would get a four-fold increase.

        1. memory can be much wider than 8 bit and often is to get more bandwidth, that has nothing to do with addresses being in bytes, almost all mainstream processors are, including all ARMs and PCs. Unless you have a full Harvard architecture not being able to address bytes gets messy

        2. All addressing in ARMs is by bytes. A 16 bit Thumb instructions 2 “addresses” long – 2 bytes. You have to increment the PC by 2 to get the next instruction. 32 bit ARM instructions are 4 “addresses” long. Changing bus width does not change the size of the address space needed for the code. So, I don’t follow the point or I’m missing something.

    1. A53 is an armv8 architecture but it is 64-bit. And yes it is supposedly the successor of the A7 which is a 32-bit armv7 architecture.

      A32 is supposed to be an armv8 architecture and 32-bits. ARM wants to continue producing newer versions of its 32-bit cores as they tend to be more power efficient than the 64-bit versions.

  5. Maybe if you actually wrote or linked to an article which explained the relative merits and drawbacks of implementation in hardware via peripherals and software you could actually put these silly bus width arguments to rest.

    Of course, I don’t actually expect you do do anything other than plug the latest products and perpetuate the stupidity.

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