Vulcan 74: A Masterpiece of Retro Engineering

[Radical Brad] has played around with FPGAs, video signals, and already has a few astonishing projects of bitbanged VGA on his resume. Now he’s gone insane. He’s documenting a build over on the 6502.org forums of a computer with Amiga-quality graphics built out of nothing but a 65C02, a few SRAM chips, and a whole pile of logic chips.

The design goals for this project are to build a video game system with circa 1980 parts and graphics a decade ahead of its time. The video output is VGA, with 400×300 resolution, in glorious eight-bit color. The only chips in this project more complex than a shift register are a single 65c02 and a few (modern) 15ns SRAMs. it’s not a build that would have been possible in the early 80s, but the only thing preventing that would be the slow RAM chips of the era.

So far, [Radical] has built a GPU entirely out of 74-series logic that reads a portion of RAM and translates that to XY positions, colors, pixels, and VGA signals. There’s support for alpha channels and multiple sprites. The plan is to add sound hardware with support for four independent digital channels and 1 Megabyte of sample memory. It’s an amazingly ambitious project, and becomes even more impressive when you realize he’s doing all of this on solderless breadboards.

[Brad] will keep updating the thread on 6502.org until he’s done or dies trying. So far, it’s looking promising. He already has a bunch of Boing balls bouncing around a display. You can check out a video of that below.

42 thoughts on “Vulcan 74: A Masterpiece of Retro Engineering

    1. Yes, I will be doing a dedicated website for this system, which will include schematics, PCB files, and a downloadable 300-400 page book on how every single part of the system works.

      I will also include many source codes for games and demos.

      Cheers,
      Radical Brad

  1. Like that… going through this gives sound understanding of what digital is in its core… Today we are often so far away due to the VSLI(ntegration), that we forget to appreciate what we have and how ‘easy and powerful’ (digital) hacker life is…

    1. If I had to guess, I would say it’s doing ROM emulation or he is using it to preload RAM with code to speed his development cycles. The 6502 clearly needs some persistent code storage and a ROM wasn’t called out in the BoM.

  2. Hog wash. If Radical Brad were truely my hero, he would abandon this trivial puny project and write a Verilog to 7400/4000 synthesis tool that would place and route to minimize chips and a fitter that area optimizes chip placement in the form of a EDA board file output! Then Zeus himself would rain down a thunderclap when the 6502 too was replaced by an `include “6502.v”

  3. Nitpick: A transparent color is not an “alpha channel”, it’s a specific color index that the hardware interprets as “let through whatever is behind this pixel in this sprite”. An alpha channel would mean either alpha blending, or even a specific bit in the sprite’s color data that flags the pixel as being fully transparent. A specific color index that inhibits a color write is not, nor has it ever been an “alpha channel”.

    1. That’s debatable. A bob is by definition drawn using a blitter. Unless that pile of 74-series logic chips possesses a command set that I’m not aware of, they’re standard sprites. They’re no more bobs than the sprites of classic arcade games in the late 70’s and early to mid 80’s that were also drawn with standard 74-series logic and not ASICs.

    1. Indeed, excellent (and very clean breadboarding) work!

      For those who have not read the blog posts, I can highly recommend it… it gives much more insight into what is happening and why (and how he is using / abusing the various logic chips to do what is desired).

      1. Thanks for the comments!

        Since I made this video, I have expanded the board quite a bit, and increased overall performance.
        I now have another 1024K doing a large scrollable bitmap transfers at the start of every frame.
        This is called “The Playfield”, and can be 512×2048, 1024×1024, or 2048×512 in size.

        I will probably start on the 6502 decode logic in a few days and then look for a dozen more breadboards to start prototyping the sound system. You can NEVER have a large enough board, dude.

        Cheers!
        Radical Brad

  4. If he has any intermittent problems with his logic, the first thing I would do is to untie all the wrapped bundle of wires – that is just begging for cross-coupling of signals, especially on clock lines.

    1. 20MHz throughout the entire board and no glitches yet.
      Wiring is wrapped us bus line bundles, with opposing signals kept at a fair distance from each other.
      It’s more than just a pretty board, there is a small degree of sanity to the layout.

      When I finally get around to making a real PCB, it will be easy.

      Radical Brad

      1. A word of caution – I ran into a problem with busses on a PCB when I did my first bit slice disk controller [AMD 2900 series around 1975] – I had the main 8 bit data bus running parallel to a r/s flip flop line which was next to a ground trace – every time more than 5 of the 8 lines transitioned from high to low, they would couple enough into the r/s flip flop line to reset the flip flop.

  5. Very cool! Is there a description of the hardware sprites in any detail? I’ve just finished working out my FPGA VGA text mode, with the output being assembled from character rom, screen memory and attributes. I can see how you would do a bitmap display, shifting it out, but I don’t see how you would do arbitrary sprites in hardware without a silly number of registers… or is there some kind of copperish thing with the display asking the CPU if it wants a sprite on this line during the HBL?

    1. +1, I would also like to see some schematics showing how the sprites are done.

      I have started something similar with very small CPLD. It’s here –
      https://hackaday.io/project/3610-z80-retro-computer-with-graphics

      Where is your project [Howard Jones], Link please?

      @[Brad] I ended up using the 800×600@50Mhz (72Hz) standard but at half clock – 400×300@25MHz because I had trouble finding 25.175MHz Active Oscillators and 50/100MHz are easy to find. My design is only a BMP like output – no sprites, so I would be very interested to see how you did the sprites. The really old retro games usually only had a background (often a scrolling image) a foreground image (for game play). The CPLD I am using has only about 400 registers.

      And what did you do in a previous life to deserve this lol. Just jokes. I am easily able to resist the temptation of turning my CPLD design into a 74xx career.

      1. I will have to write something up! The actual project is to try and get a proper old-school instant-on vt100 style serial terminal with one of those $30 CycloneII mini boards.

        Having read some more of [Brad]’s thread, I can see that it’s actually more like an automated blitter assembling the back buffer before the display controller displays it. There’s a really nice write up of a similar design (but Xilinx FPGA not 74 logic) here: http://andybrown.me.uk/wk/2014/06/01/ase/

    2. They aren’t really sprites, but Blitter objects. There are two video buffers, and while the display generator is showing the first one, the blitter copies rectangular objects into the second one. The CPU sets up the coordinates of each objects, and the address of the source data.

      This requires much less complicated hardware than real hardware sprites. It does however require you to redraw the background for every frame.

  6. What was the fastest SRAM available in the 1980’s? I found a datasheet for Intel D2147H 4096×1 bit with the fastest speed as 45ns.

    Has me thinking of a line interleave mode with 2 banks of SRAM, with each bank holding half the lines – some way to effectively double the speed of the SRAM by using twice as much, using half the chips’ capacity and interleaving the cycles. During non-motion screens the display resolution could be increased by using all the SRAM in a single bank, non-interleaved mode.

  7. Impressive project! However, the “design goal” seems a bit lost:

    “The design goals for this project are to build a video game system with circa 1980 parts and graphics a decade ahead of its time.”

    While it may use a 6502 and 74-logic – in case some are wondering why something like this wasn’t done back in the 80s. No they weren’t overlooking something: the real contraint of such a (gaming-) system in the 80s was memory. Memory was usually the single most expensive resource, and memory constraints were the reason backgrounds consisted of a block of indices into 8×8 pixel blocks, why color indexing (a palette) was used, ultimately leading to the more complex chips such as the VIC-II (C64), VDP (Sega), PPU (Nintendo), etc. These systems typically used only a few kilobytes of memory to create the full image. This was the “magical” thing these VDP’s did, as well as generating all this on the fly (including sprites) as the video trace flew by, without a framebuffer.

    By removing this main constraint using today’s cheap memory, creating an image on the screen becomes a LOT simpler. This is why it can be done (as shown) using some 74-logic – you basically only need some counters to implement a crude form of DMA (copying blocks of memory from one location to another). It’s still impressive of course, but it’s important to view it in the right context.

    1. Agreed, but there was also another edge to the sword. The CPUs of the era were not even 1MIPs. Having a large amount of video memory would result in the CPU being too slow to update it all. So other techniques like tiles were used. One tile was 32 to 128 Bytes of ram but the CPU only had to write one byte to change the tile. This gave the CPU quite some leverage over the Video RAM AND it requires less RAM to implement a frame.

      If it were just the cost issue then there would have been some expensive computers with large video RAMs. There were some computers with more RAM like the Amega’s but they had a well designed system for the CPU to leverage time and also much faster CPU’s

      1. Absolutely: the performance is of course another reason to use the tile-based approach, as you only have to update some indices, e.g. while scrolling. But as this example is using a 6502, I’m assuming he’s using it at a low frequency as well (like 1 or 2 MHz), so this is not something he ‘cheated’ on by taking advantage of the progress made there since the 80s. The other thing is performance of the memory itself, which was mentioned in the article. But what wasn’t really mentioned was the *amount* of memory, which is the most significant departure from the “design goal”, which is why I mentioned it above :) Not that you couldn’t have megabytes of RAM back in the early 80s: it just would have been very (and prohibitively, for a game system) expensive.

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