New Part Day: A 64-Bit RISC-V CPU In Raspberry Pi Hat Form

Over the last few years the open-source RISC-V microprocessor has moved from existing only on FPGAs into real silicon, and right now you can buy a RISC-V microcontroller with all the bells and whistles you would ever want. There’s an interesting chip from China called the Sipeed M1 that features a dual-core RISC-V core running at 600MHz, a bunch of I/Os, and because it’s 2019, a neural network processor. We’ve seen this chip before, but now Seeed Studios is selling it as a Raspberry Pi Hat. Is it an add-on board for a Pi, or is it its own standalone thing? Who knows.

The Grove AI Hat for Edge Computing, as this board is called, is built around the Sipeed MAix M1 AI Module with a Kendryte K210 processor. This is a dual-core 64-bit RISC-V chip and it is obviously the star of the show here. In addition to this chip you’ve also got a few Grove headers for digital I/O, I2C, PWM, and a UART. There’s a a USB Type C for power (finally we’re getting away from USB micro power plugs), and of course a 40-pin Raspberry Pi-style header.

This board is essentially a breakout board for the Sipeed M1 chip, which is one of the most interesting new microcontrollers we’ve seen since it launched late last year. There’s a lot of power here, and already people are emulating the Nintendo Entertainment System on this chip with great success. The problem with this chip is that apart from making your own breakout board, there aren’t many options to get it up and running quickly. This is the solution to that; at the very least it’s a Sipeed chip on a board with a power supply, and it’s also a co-processor that can be accessed with Linux and a Raspberry Pi.

30 thoughts on “New Part Day: A 64-Bit RISC-V CPU In Raspberry Pi Hat Form

  1. ” There’s an interesting chip from China called the Sipeed M1 that features a dual-core RISC-V core running at 600MHz, a bunch of I/Os, and because it’s 2019, a neural network processor. ”

    And now we know what Huawei will be using. :-D

          1. Well, if you’d looked at thrangrycat, you’d know! Kidding. PLA = programmable logic array. FPGA’s are PLA’s used for hardware development. So a bunch of components in a grid wired together by a grid of logic, and which logic it is is and which components are wired to it is determined by which points on a grid are connected or not, which are determined by a bitstream that is fed in, usually through a separate device called a jtag unit, although some stuff has onboard jtag units now, and even servers with oscilloscope stuff. is the site of the person Steven is recommending it looks like (which, thanks Steven! I bought an fpga device not long ago(tang nano 9k) and will look into this person). Typically rather than coming up with a bitstream to write to an fpga you’d write in a language like VHDL or verilog and let the machine synthesize it into your binary string and load it to the jtag unit (and onto your fpga). So hacking the bits seems a step harder and more interesting, to me, than the normal verilog I guess. (I dunno if i’m explaining stuff you know and you’re just having a laugh or not but if helpful there is what little I know about it)

      1. To take the Pi out of the loop for feature recognition applications. Camera->Pi->coprocessor takes more energy than letting the coprocessor get frames directly from the camera, plus lets you put the Pi to sleep while waiting for an interesting image.

    1. One reason for considering the Sipeed M1 chipset is it’s features. The story talks about the dual core and RISC processor, but it also has an FFT, floating point, audio, video coprocessor built onto the chip as well as a knowledge processing unit (KPU) that is designed to run a neural network. The hat can off load a lot of work and you could easily pair it up with a PI zero… and oh yeah, it has an SHA256 coprocessor and some of the M1 chipsets have wifi…

    2. the “Sipeed Maixduino Kit for RISC-V AI + IoT” on seeed comes with an integrated ESP32 module for wifi and bluetooth, a screen and a camera for 24$ to preorder…

  2. Seeeeed also has the R3399Pro with inbuilt neural net and external RAM for the net processor. 4 times the price, and probably 20 times the performance. For when you need to get all neural netty because, AI.

  3. Hackaday, you forgot to mention why the chipset is called “Sipeed MAix M1 AI Module” E.g. why it has AI in the name. This chipset has an onboard FFT, floading point processing, SHA256 support, memory, coprocessing for audio (8 channels of audio, 192k/second), video coprocessor, standard I2C, and the AI – well that comes from the knowledge processing unit (KPU) which implements a neural network.

    1. Hackaday actually did explain that it has a neural work — but lots of the commentators to the story have missed why that’s different than an ordinary raspberry PI. That built in neural network support — plus the other features – as a hat… speeds up applications written for a PI that can be offloaded to the hat functions. For example facial recognition is fast… and can be done without burning cycles on the PI.

    1. The chipsets PI & Arduino modules allow software to be loaded directly onto the hat/shield. MaxPy is a microPython adapted specifically for this AI chip with libraries that support the neural network, object recognition etc. They also support (as noted below) the IDEs that are typically used for the Arduino or PI. You can split the work for your project into two parts – the code that runs on the AI hat/shield down load it onto the hat/shield… select your pins or methods to talk to the base sheild (or use wifi) and communicate…

      From the M1 chipset description:

      Support MaixPy IDE, Arduino IDE, OpenMV IDE, and PlatformIO IDE
      Support Tiny-Yolo, Mobilenet and TensorFlow Lite for deep learning

    1. No. The term “RISC” describes a “style” of CPU architecture (Reduced Instruction Set Computer vs CISC or Complex Instruction Set Computer – like x86 is), not a specific type of CPU. RISC-V and PowerPC are both “RISC style” architectures, but not compatible (quite different specific instruction sets).

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