The greatest hardware hacks of all time were simply the result of finding software keys in memory. The AACS encryption debacle — the 09 F9 key that allowed us to decrypt HD DVDs — was the result of encryption keys just sitting in main memory, where it could be read by any other program. DeCSS, the hack that gave us all access to DVDs was again the result of encryption keys sitting out in the open.
Because encryption doesn’t work if your keys are just sitting out in the open, system designers have come up with ingenious solutions to prevent evil hackers form accessing these keys. One of the best solutions is the hardware enclave, a tiny bit of silicon that protects keys and other bits of information. Apple has an entire line of chips, Intel has hardware extensions, and all of these are black box solutions. They do work, but we have no idea if there are any vulnerabilities. If you can’t study it, it’s just an article of faith that these hardware enclaves will keep working.
Now, there might be another option. RISC-V researchers are busy creating an Open Source hardware enclave. This is an Open Source project to build secure hardware enclaves to store cryptographic keys and other secret information, and they’re doing it in a way that can be accessed and studied. Trust but verify, yes, and that’s why this is the most innovative hardware development in the last decade.
Continue reading “RISC-V Will Stop Hackers Dead From Getting Into Your Computer”
If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using, say, a C compiler is to machine language or assembly code. There are other challengers to the throne such as SpinalHDL which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL to make an extremely flexible system that is as efficient as plain Verilog. He says the example really shows off why you should be using SpinaHDL.
Like a conventional programming language, it is easy to find niche languages that will attract a little attention and either take off (say, C++, Java, or Rust) or just sort of fade away. The problem is you can’t ever tell which ones are going to become major and which are just flashes in the pan. Is SpinalHDL the next big thing? We don’t know.
Continue reading “VexRISC-V Exposed”
One of the ways people use FPGAs is to have part of the FPGA fabric hold a CPU. That makes sense because CPUs are good at some jobs that are hard to do with an FPGA, and vice versa. Now that the RISC-V architecture is available it makes sense that it can be used as an FPGA-based CPU. [Clifford Wolf] created PicoSOC — a RISC-V CPU made to work as a SOC or System on Chip with a Lattice 8K evaluation board. [Mattvenn] ported that over to a TinyFPGA board that also contains a Lattice FPGA and shows an example of interfacing it with a WS2812 intelligent LED peripheral. You can see a video about the project, below.
True to the open source nature of the RISC-V, the project uses the open source Icestorm toolchain which we’ve talked about many times before. [Matt] thoughtfully provided the firmware precompiled so you don’t have to install gcc for the RISC-V unless you want to write you own software. Which, of course, you will.
Continue reading “RISC-V CPU Gets A Peripheral”
Here’s something of interest of 3D printing enthusiasts. How do you print lightweight 3D objects? [Tom Stanton] does a lot of stuff with 3D printing and RC airplanes, so yeah, he’s probably the guy you want to talk to. His solution is Simplify3D, printing two layers for whatever nozzle diameter you have, some skills with Fusion360, and some interesting design features that include integrated ribs.
Moog released their first polyphonic analog synth in 35 years. It’s massive, and it costs eight thousand dollars.
There’s a RISC-V contest, sponsored by Google, Antmicro, and Microchip. The goal is to encourage designers to create innovative FPGA and soft CPU implementations with the RISC-V ISA. There are four categories, the smallest implementation for SpartFusion2 or IGLOO2 boards, and the smallest implementation that fits on an iCE40 UltraPlus board. The two additional categories are the highest performance implementation for these boards. The prize is $6k.
” I heard about polarization filters and now I’m getting a hundred thousand dollars” — some moron. IRL Glasses are glasses that block screens. When you wear them, you can’t watch TV. This is great, as now all advertising is on TVs for some inexplicable reason, and gives these people an excuse to use frames from John Carpenter’s masterpiece They Live in their Kickstarter campaign. Question time: why don’t all polarized sunglasses do this. Because there’s a difference between linear and circular polarized lenses. Question: there have been linear polarized sunglasses sitting in the trash since the release of James Cameron’s Avatar. Why now? No idea.
Alexa is on the ESP32. Espressif released their Alexa SDK that supports conversations, music and audio serivces (Alexa, play Despacito), and alarms. The supported hardware is physically quite large, but it can be extended to other ESP32-based platforms that have SPI RAM.
We were contacted by [morbo] to let us know about a project on the AdaCore blog that concerns programming a PicoRV32 RISC-V softcore with Ada. The softcore itself runs on a Lattice ICE40LP8K-based TinyFPGA-BX FPGA board, which we have covered in the past.
The blog post describes how to use the Community edition of the GNAT Ada compiler to set up the development environment, before implementing a simple example project that controls a strip of WS28212b RGB LED modules. There are two push buttons changing the animation and brightness of the lights.
The source can be found at the author’s Github repository, and contains both the Ada source and the Verilog source for the PicoRV32 softcore. To build the project one needs the GNAT compiler, as well as the open-source iCE40 development tools to compile the softcore.
There is a video demonstrating the finished example project, that we’ve placed below the break.
Continue reading “Programming A RISC-V Softcore With Ada”
After exploring a few random online shops one day, [David] (thanks for sending this in, by the way) ran across a very interesting chip. It’s a dual-core, RISC-V chip running at 400MHz. There’s 6 MB of SRAM on the CPU, and there’s 2MB for convolutional neural network acceleration. There is, apparently, WiFi on some versions. There are already SDKs available on GitHub, and a bare chip costs a dollar or two. Interested? Log in to Taobao, realize Taobao does pre-orders, and all this can be yours.
This is a preorder — because apparently you can do that as a seller on TaoBao, but the Sipeed M1 K210 is available as a ‘core’ board with 72 pins in a one-inch square package, a version with WiFi, or as a complete development board with an OV2640 camera, 2.4 inch LCD, microphone, and onboard USB. There are videos of this chip running a face detection routine. It found Obama.
A bit of googling tells us this chip comes from a company named Kendryte, and here the specs are repeated: this is a dual-core RISC-V with an FPU, a bunch of RAM, and can run TensorFlow. Documentation is available, although the datasheet will need to be translated, and as of this writing there’s a GitHub filled with SDKs and examples, with some of the repos updated in the last hour.
Over the years we’ve seen a few RISC-V chips given development boards, and you can buy them right now. The HiFive 1 is an exceptionally powerful microcontroller with processing power that puts it right up against the Teensy (which is built around a Freescale chip), but it’s also fairly expensive. We’re not sure the Arduino Cinque (also RISC-V) ever made it to production, but again, expensive. The idea that a RISC-V microcontroller could be available for just a few dollars is very interesting, it even comes with SDKs and utilities to make the chip useful.
Have you tried Altium CircuitMaker? Uh, you probably shouldn’t. [Dave] of EEVBlog fame informs us via a reliable source that CircuitMaker is intentionally crippled by adding a random sleep on high pad-count boards. The hilarious pseudocode suggested on the forum is
if ((time.secs % 3) == 0) delayMicroseconds(padCount * ((rand() % 20) + 1));.Now, this is a rumor, however, I would assume [Dave] has a few back channels to Altium. Also, this assertation is supported by the documentation for CircuitStudio, which says, “While there are no ‘hard limits’ per se, the software has been engineered to make it impractical for use with large designs. To this end, the PCB Editor will start to exibit [sic] performance degradation when editing designs containing 5000 pads”. Chalk this up to another win for Fritzing; Fritzing will not slow down your computer on purpose.
Here’s an open challenge to everyone. As reported by [SexyCyborg], XYZPrinting (makers of the da Vinci printer) are patent trolling. This US patent is being used to take 3D printers off of the Amazon marketplace. Here’s the problem: no one can figure out what this patent is actually claiming. There’s something about multiple nozzles, and it might be about reducing nozzle travel, but I’m getting a ‘snap to bed’ vibe from this thing. Experts in 3D printing have no idea what this patent is claiming. The printer in question is the Ender 3, one of the first (actually the third…) China-based Open Source Hardware certified products, and it’s actually the best selling printer on Amazon at this time. I’m talking with Comgrow (the sellers of the Ender 3 on Amazon), and the entire situation is a mess. Look for an update soon.
Tired: Congress shall make no law… abridging the freedom of speech. Wired: But what if that speech is a gun? Wired‘s own Andy Greenberg advances the argument that computer code is not speech, contrary to many court rulings over the past 30 years (see Bernstein v. United States). Here’s the EFF’s amicus brief from the case. Read it. Understand it. Here’s a glowing Stephen Levy piece from 1994 on the export-controlled PGP for reference.
Like integrated circuits and microprocessors? Sure you do. Like drama? Oh boy have we got the thing for you. A week or so ago, ARM launched a website called RISC-V Basics (now unavailable, even from the Internet Archive, but you can try it here). It purports to settle the record on those new chips based on the capital-O Open RISC-V instruction set. In reality, it’s a lot of Fear, Uncertainty, and Doubt. This was an attempt by ARM Holdings to kneecap the upstart RISC-V architecture, but a lot of ARM engineers didn’t like it.