Compute Like It Is 1975: 6th Edition Unix Reborn

If you crave experiencing or reliving what computing was like “back then” you have a lot of options. One option, of course, is to load an emulator and pretend like you have the hardware and software you are interested in. Another often expensive option is to actually buy the hardware on the used market. However, [mit-pdos] has a different approach: port the 6th edition of Unix to RISC-V and use a modern CPU to run an old favorite operating system.

It isn’t an exact copy, of course, but Xv6 was developed back in 2006 as a teaching operating system at MIT. You can find resources including links to the original Unix source code, commentary on the source code, and information about the original PDP 11/40 host computer on the project’s main page.

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Homebrew RISC-V Computer Has Beauty And Brains

Building your own CPU is arguably the best way to truly wrap your head around how all those ones and zeros get flung around inside of a computer, but as you can probably imagine even a relatively simple processor takes an incredible amount of time and patience to put together. Plus, more often than not you’re then left with a maze of wires and perfboards that takes up half your desk and doesn’t do a whole lot more than blink some LEDs.

An early prototype of the Pineapple ONE.

But the Pineapple ONE, built by [Filip Szkandera] isn’t your average homebrew computer. Oh sure, it still took two years for him to design, debug, and assemble, his 32-bit RISC-V CPU and all its associated hardware; but the end result is a gorgeous looking machine that runs C programs and offers a basic interactive shell over VGA. In fact with its slick 3D printed enclosure, vertically stacked construction, and modular peripheral connections, it looks more like some kind of high-tech scientific instrument than a computer; homebrew or otherwise.

[Filip] says he was inspired to build this 500 kHz (yes, kilohertz) beauty using only discrete logic components by [Ben Eater]’s well known 8-bit  breadboard computer and [Robert Baruch]’s LMARV-1 (Learn Me A RISC-V, version 1). He spent six months simulating the machine before he even started creating the schematics, let alone design the individual boards. He tried to keep all of his PCB’s under 100 x 100 mm to take advantage of discounts from the fabricator, which ultimately led to the decision to align the nine boards vertically and connect them together with pin headers.

In the video below you can see [Filip] start up the computer, call up a bit of system information, and even play a rudimentary game of snake before peeking and poking some of the machine’s 512 kB of RAM. It sounds like there’s still some work to be done and bugs to squash, but we’ve already seen enough to say this machine has more than earned entry into the pantheon of master-crafted homebrew computers.

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Exploring The Open Source That Really Goes Into A RISC-V Chip

It’s an exciting time in the world of microprocessors, as the long-held promise of devices with open-source RISC-V cores is coming to fruition. Finally we might be about to see open-source from the silicon to the user interface, or so  goes the optimistic promise. In fact the real story is considerably more complex than that, and it’s a topic [Andreas Speiss] explores in a video that looks at the issue with a wide lens.

He starts with the basics, looking at the various layers of a computer from the user level down to the instruction set architecture. It’s a watchable primer even for those familiar with the topic, and gives a full background to the emergence of RISC-V. He then takes Espressif’s ESP32-C3 as an example, and breaks down its open-source credentials. The ISA of the processor core is RISC-V with some extensions, but he makes the point that the core hardware itself can still be closed source even though it implements an open-source instruction set. His conclusion is that while a truly open-source RISC-V chip is entirely possible (as demonstrated with a cameo Superconference badge appearance), the importance of the RISC-V ISA is in its likely emergence as a heavyweight counterbalance to ARM’s dominance in the sector. Whether or not he is right can only be proved by time, but we can’t disagree that some competition is healthy.

Take a closer look at the ESP32-C3, with our hands-on review.

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ESP32-S2 And RP2040 Hack Chat With Adafruit

Join us on Wednesday, January 27 at noon Pacific for the ESP32-S2 and RP2040 Hack Chat with Adafruit!

It’s always an event when we have Adafruit on the Hack Chat, and last time was no exception. Then, the ESP32-S2 was the new newness, and Adafruit was just diving into what’s possible with the chip. It’s an interesting beast — with a single core and no Bluetooth or Ethernet built-in, it appears to be less capable than other Espressif chips. But with a faster CPU, more GPIO and ADCs, a RISC-V co-processor, and native USB, the chip looked promising.

Among their other duties, the folks at Adafruit have spent the last six months working with the chip, and they’d now like to share what they’ve learned with the community. So Limor “Ladyada” Fried, Phillip Torrone, Scott Shawcroft, Dan Halbert, and Jeff Epler will stop by the Hack Chat to show us what’s under the hood of the ESP32-S2. They’ve worked on a bunch of projects using the chip, and they’ve taken a deep-dive into the chip’s deep-sleep capabilities, so stop by the Chat with your burning questions about low-power applications or anything ESP32-S2-related and ask away.

Plus, a late and exciting addition to the agenda: they’ll be talking about the recently released RP2040, the first custom chip from the folks at Raspberry Pi. We’ve already started talking about the Raspberry Pi Pico​, the dev board that uses the chip, and Adafruit will share what they’ve learned about the RP2040 so far.

join-hack-chatOur Hack Chats are live community events in the Hackaday.io Hack Chat group messaging. This week we’ll be sitting down on Wednesday, January 27 at 12:00 PM Pacific time. If time zones have you tied up, we have a handy time zone converter.

Click that speech bubble to the right, and you’ll be taken directly to the Hack Chat group on Hackaday.io. You don’t have to wait until Wednesday; join whenever you want and you can see what the community is talking about.

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RISC-V Comes To The BeagleBoard Ecosystem With Upcoming Beagle V SBC

The Beagle V, a RISC-V-based single board computer from a collaboration between BeagleBoard and Seeed Studios aims to be “The First Affordable RISC-V Computer Designed to Run Linux”. RISC-V is the open-source processor architecture that everyone is interested in because it bypasses proprietary silicon of manufacturers such as Intel or AMD, allowing companies to roll their own silicon processors without licensing fees for the core.

BeagleBoard has long been one of the major players in the Single-Board Computer arena so far dominated by the Raspberry Pi. The board, slightly larger than the company’s previous offerings, features a StarFive dual-core 64-bit RISC-V processor running at a 1.0 GHz clock speed. The spec sheet on their GitHub repo indicates 4 and 8 GB RAM options, built-in WiFi and Bluetooth, and hardware video support for decoding, two camera connectors, one DSI connector for an external display, as well as a full-sized HDMI port. Gigabit Ethernet, four USB-3 ports, an audio jack, and USB-C as the power supply are packed onto the edges of the board. GPIO is routed to a 2×20 pin header.

Seeed Studio pegs the cost of the board at $149 for the 8 GB RAM version, although currently you must apply and be selected to purchase a board in this early stage. It’s unclear if the price will remain unchanged after this first run; the product page notes a coupon code is necessary and the Seeed Studios article indicates this is an introductory price. However, the same article also lists the 4 GB RAM variant at $119. The BeagleBoard page shows a timeline of April 2021 for a “pilot run for community”.

It’s exciting to see RISC-V continue to make inroads. This is a powerful board based around the core, and if successful it will help further prove the viability of open source processing cores in increasingly mainstream products.

Pushing The FPGA Video Player Further

A fact universally known among the Hackaday community is that projects are never truly done. You can always spin another board release to fix a silkscreen mistake, get that extra little boost of performance, or finally spend the time to track down that weird transient bug. Or in [ultraembedded’s] case, take a custom FPGA player from 800 x 600 to 1280 x 720. The hardware used is a Digilent Arty A7 and PMOD boards for I2S2, VGA, and MicroSD. We previously covered this project back when it was first getting started.

Getting from 800 x 600 to 1280 x 720 — 31% more pixels — required implementing a higher performance JPEG decoder that can read in the MPJEG frames, pushing out a pixel every 2.1 clock cycles. The improvements also include a few convenience features such as an IR remote. The number of submodules inside the system is just incredible, with most of them being implemented or tweaked by [ultraembedded] himself.

For the FPGA Verilog, there’s the SD/MMC interface, the JPEG decoder, the audio controller, the DVI framebuffer, a peripheral core, and a custom RISC-V CPU. For the firmware loaded off the SD card, it uses a custom RTOS running an MP3 decoder, a FAT32 interface, an IR decoder, and a UI based on LVGL.

We think this project represents a wonderful culmination of all the different IP cores that [ultraembedded] has produced over the years. All the code for the FPGA media player is available on GitHub.

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Espressif Leaks ESP32-C3: A WiFi SoC That’s RISC-V And Is ESP8266 Pin-Compatible

Six years on from the emergence of the Espressif ESP8266 we might believe that the focus had shifted to the newer dual-core ESP32. But here comes a twist in the form of the newly-revealed ESP32-C3. It’s a WiFi SoC that despite its ESP32 name contains a RISC-V core in place of the Tensilica core in the ESP32s we know, and uses the ESP8266 pin-out rather than that of its newer sibling. There’s relatively little information about it at the time of writing, but CNX Software have gathered together what there is including a draft datasheet whose English translation is available as a Mega download. As with other ESP32 family members, this one delivers b/g/n WiFi and Bluetooth Low-Energy (BLE) 5, where it differs is the RISC-V 32 Single-core processor with a clock speed of up to 160 MHz. There is 400 kB of SRAM and 384 kB ROM storage space built in.

While there is no official announcement yet, Espressif has been dropping hints. There’s been an OpenOCD configuration file for it in the Espressif repositories since the end of last month. And on Friday, Espressif Software Engineering Manager [Sprite_tm] answered a reddit comment, confirming the RISC-V core.

ESP-01: Kjerish, CC BY-SA 4.0, RISC-V logo: RISC-V foundation, Public domain.

Why they are releasing the part as an ESP32 rather than giving it a series number of its own remains a mystery, but it’s not hard to see why it makes commercial sense to create it in an ESP8266-compatible footprint. The arrival of competing parts in the cheap wireless SoC space such as the Bouffalo Labs BL602 we mentioned recently is likely to be eating into sales of the six-year-old chip, so an upgrade path to a more capable part with minimal new hardware design requirements could be a powerful incentive for large customers to stay with Espressif.

We’re left to guess on how exactly the rollout will proceed. We expect to see similar developer support to that they now provide for their other chips, and then ESP32-C3 powered versions of existing ESP8266 boards in short order. It’s also to be hoped that a standard RISC-V toolchain could be used instead of the device-specific ones for current Espressif offerings. What we should not expect are open-source replacements for the blobs that drive the on-board peripherals, as the new chip will share the same closed-source IP as its predecessors for them. Perhaps if the PINE64 initiative to reverse engineer blobs for the BL602 bears fruit, we might see a similar effort for this chip.