Retrocomputers need ROMs, but they’re just so read only. Enter the latest incarnation of [Piers]’s One ROM to rule them all, now built with a RP2350, because the newest version is 5V capable. This can replace the failing ROMs in your old Commodore gear with this sweet design on a two-layer PCB, using a cheap microcontroller.
[Piers] wanted to use the RP2350 from the beginning but there simply wasn’t space on the board for the 23 level shifters which would have been required. But now that the A4 stepping adds 5 V tolerance [Piers] has been able to reformulate his design.
The C64 in the demo has three different ROMs: the basic ROM, kernel ROM, and character ROM. A single One ROM can emulate all three. The firmware is performance critical, it needs to convert requests on the address pins to results on the data bus just as fast as it can and [Piers] employs a number of tricks to meet these requirements.
The PCB layout for the RP2350 required extensive changes from the larger STM32 in the previous version. Because the RP2350 uses large power and ground pads underneath the IC this area, which was originally used to drop vias to the other side of the board, was no longer available for signal routing. And of course [Piers] is constrained by the size of the board needing to fit in the original form factor used by the C64.
The One ROM code is available over on GitHub, and the accompanying video from [Piers] is an interesting look into the design process and how tradeoffs and compromises and hacks are made in order to meet functional requirements.
Thanks to [Piers] for writing in to let us know about the new version of his project.
Why would you use 2-layer today when 4-layer boards are practically free?
Well, 5V tolerant but not like this. From the RP2350 data sheet:
Fault Tolerant Digital. These pins are described as Fault Tolerant,
which in this case means that very little current flows into the pin
whilst it is below 3.63 V and IOVDD is 0 V. Additionally, they will
tolerate voltages up to 5.5 V, provided IOVDD is powered to 3.3 V.
Since the 3.3V regulator runs off the 5V in this design there is plenty of time for 5V to fry your GPIOs before the IOVDD is up and stable at 3.3V.
Will it work anyway? Maybe, probably, who knows? It’s not to spec anyway.
Nice work. I especially appreciate the work on /reading/ the data sheet to find exploitable behaviors. FWIW, it might be fine to put bypass caps on the backside of the board as the legs of the ROM may be made long enough to reach.
Amazing a dual core (quad core?) multiple hundred Mhz SoC and its PCB are cheaper than a PROM now!
Any chance you can add peripherals or virtual drives on the ROM socket of these systems?