Propeddle, The Software Defined 6502

propeddle

When it comes to building retrocomputers, there are two schools of thought. The first is emulation, that allows for greater compatibility and ease of use, and much easier to find parts. The second requires real, vintage hardware with all the bugs and idiosyncrasies found in vintage chips. Reconciling these two ideas is hard, but the software defined Propeddle manages to do it, all while using a real 6502 CPU.

The trick here is using a Parallax Propeller for the heavy lifting of loading the ROM into RAM with an extremely clever technique using the Reset and NMI pins, generating the clock and other signals required by the 6502, and hosting the keyboard, serial, and video I/O. Already [Jac] has the Propeddle running as an Apple 1 emulator (video below), making it possible to write programs for the Propeddle in BASIC or assembly.

It’s a great design that allows for emulation of a lot of the classic 6502 computers with a real CPU, all while doing away with the cruft of expensive ACIAs and video generation hardware. Awesome work, and we can’t wait for the next version that will be dedicated to [Bill Mensch].

Comments

  1. Jake says:

    And getting it onto the retro site?

    • Jac Goudsmit says:

      Getting Propeddle onto the Retro site is a matter of software (just like accomplishing pretty much everything else). The simplest way to show the HAD retro website would probably be to run the terminal test program (not shown in the video) and connecting the serial port to a Linux computer running Links. That’s so trivial to do, it’s almost not worth it, and also it’s a bit like cheating because the heavy work is really done by another computer.

  2. zuul says:

    propeddle hah

  3. LIV2 says:

    If he uses the 65C02 (which is a good idea since the 65c02 fixes a bunch of things) he could make use of the Bus Enable pin which allows you to disable the cpu’s bus buffers which would make copying rom to ram easier.

    • Jac Goudsmit says:

      I considered doing that. There’s just one problem: the data bus and address bus are multiplexed onto the same pins of the Propeller. If I would want to let the Propeller control the address bus directly, it would require at least two more chips to latch the address from the Propeller.

      The way it works now, the Propeller generates an NMI (or Reset) and then intercepts the clock cycles where the 6502 reads the vector. The 6502 starts executing the interrupt handler (or reset handler) and during the first half of each 6502 clock cycle, the Propeller can access the SRAM chip to read or write data to it. During the second half of the clock cycle, the Propeller puts a dummy instruction on the data bus which makes the 6502 generate consecutive addresses until it sees an RTI (return from interrupt). I could have thought of that myself, but credit for that algorithm goes to Dennis Ferron who used it in his Prop-6502 project.

      • LIV2 says:

        Ahh right, makes sense! Good work man!
        I’m currently building my own 6502 computer too, currently using only discrete logic but I’m sure I’m gonna need something like a propeller to do Video.

      • AussieTech says:

        Good one. I’m only surprised that this “extremely clever technique” hasn’t been more widely used. Some years ago I devised a similar all-logic hardware loader for a very minimal Z80+SRAM SBC, single stepping the Z80 to generate the address and Write signals as the RAM was loaded with the object code via the dual-port data buss, handshaking from a Centronics printer port. Much quicker than erasing/burning UV-EPROMS and a viable way of starting with zero firmware. +1 guys.

  4. Waterjet says:
  5. Sweeney says:

    Or there’s option 3, implement the original logic in an FPGA where you can get cycle accurate timings, all the original quirks, VGA video out and precise emulation of sound and video chips.

  6. Jac Goudsmit says:

    Thanks for featuring my project, Hackaday!

  7. JIm B says:

    Inspiring project, Jac. I bought one of those simple propeller experimenter boards a few months ago, but so far it is just been lounging about in the desk drawer with my other development boards, waiting until the project queue gets low enough to try something new. I’ve always respected the propeller folks for trying something different, and have been watching with dismay a the course taken by the development of the propeller II.

  8. k says:

    Great stuff! It even looks like it came out of the 80s, with the big dip chips :) Did you see the SID emulation stuff on propeller exchange?

  9. Bob says:

    HELP!!!

    I want to make a project like this with a Z80 at the core.

    I have looked at just about all the options like FPGA, Software emulation of the Z80 instruction set on a modern fast micro-controller etc.

    My main requirements –
    – Costs down!
    – Modern Z80 running at 20MHz
    – better graphics resolution than the old retro computers – perhaps QVGA
    – More RAM (SRAM) 128K or more but not excessive.
    – standard VGA timing so a ‘normal’ monitor can be used
    – either PS2 or USB keyboard and mouse
    – NO old stock parts!
    – All DIL parts or SMD to DIL adaptors for needed parts like perhaps CPLD’s
    – File storage on a SD card formatted FAT32 so data / programs are portable to windows / internet etc.

    For USB a modern micro controller can be used as an interface to the Z80.
    Page / Bank switching for the extra RAM – even some retro computers did this.

    I decided not to use ANY FPGA because as soon as you have ANY FPGA then the most economical solution is to put everything except perhaps RAM on the FPGA.

    Where I am stuck is designing a solution for the (Q)VGA output without FPGA.

    I have been looking around at CPLD’s. I haven’t worked with CPLD’s for a long time and I am ‘out of touch’ with what is available.

    I was looking at something like this (XC9572XL on DIL breakout) to cut my teeth again on CPLD’s.
    http://www.seeedstudio.com/depot/XC9572XL-CPLD-development-board-v1b-p-799.html

    I want to implement tile / palette based graphics with 6845 like registers to facilitate fast register based scrolling without loading the Z80 up with having to deal with a BMP like display output.

    I am looking at the above CPLD as a starting point because I already use Xilinx ISE for FPGA and it has schematic entry which I would prefer for something as simple as a CPLD (I am a beginner at VHDL).

    Obviously 72 Macro cells is not enough but I can’t seem to find much in the way of CPLD that is 5 Volt tolerant and can work with a Z80.

    The video path will have several RAM reads per pixel but that shouldn’t be an issue with the speed of CPLD’s and modern SRAM.

    Z80 writes tile number to RAM location that maps to a position on screen.
    This tile number points to a character location that has has a 8×8 or 16×16 BMP that is 4 or more bits deep and that in turn points to a palette.

    Z80 selects tile / character / palette with bank switching on the video generator side through a smaller memory port like 8 to 16 KBytes in the Z80’s small 64 KBytes addressing space.

    I am thinking that I need 300 – 800 Macro cells or in other words, up to 100 Bytes of registers. Probably not as far as 100 Registers but I won’t know until I decide on the end format.

    So if you have some knowledge you can spare for me –

    I am looking for a CPLD with around this range of Macro cells that is 5 Volt tolerant and is available on a DIL breakout that perhaps includes a JTAG connector.

    Something that is easy for others to solder in and to program without buying expensive programming tools or installing a full blown IDE/ISE.

    I have no particular preference to Xilinx, they don’t seem to have anything suitable that is not in obsolescence.

    Any help appreciated, thanks in advance.

    • TheCrazyRichard says:

      I’d just tell you one thing.
      Check your requirements again.

      You want a low cost device with a ton of RAM and peripherals, and hell, you even wanna use a dualport RAM in there and draw QVGA without an FPGA…
      And yet all in DIL/breakouts without old parts and all running at 5V. Hmm…

      First of all, why don’t you want to put all stuff into the FPGA, except the RAM + VRAM?
      That is indeed probably the most economical solution, and you don’t have to deal with old devices running at 5V. Seriously, nothing runs at 5V these days.
      Ok, seen some lattice FPGA that still did accept 5V inputs, but I can’t remember its name.

      Idk

      Richard

      • Bob says:

        Maybe I should have mentioned some of the other desired features. The last post was long enough as it was.

        I want something that can be used as a beginners kit. So 0.1″ spacing where possible, easy to solder/assemble and easy to ‘understand’. The 0.1″ doesn’t necessarily all need to be DIP. For example a 0.1″ ‘square’ pattern would be more suitable around a CPLD. The actual board could have pads for the surface mount and also pads for a socket for a CPLD that has been pre-programed and fitted to a 0.1″ adaptor. I was hoping to also have the same pre-mounted but non-programmed CPLD on an adaptor with JTAG for those who want to brave programming a CPLD themselves, or for supplies to do the same.

        And as mentioned without the need for expensive programmers or complex IDE’s for the end user.

        Yes I agree that one big FPGA is the simple solution but in the end you have a board with a regulator, square blob, connectors, some filter caps and some R/2R DACs that does nothing to help conceptualise what a basic computer is.

        The cost factor is more about outlay than cost and hence the choice of I/O and storage devices that most people have lying around anyway.

        The RAM isn’t that much 128 KBytes is one simple 32 Pin DIP chip. No VRAM/DRAM or dual port but instead clever bus timing so that the VDC (also in the CPLD) and CPU can share the bus time to the SRAM. A tile based video output is both RAM economical and easy on MIPS for the CPU without using up too much addressing space of the 16 Bit address bus.

        The system clock can be fed to the CPLD and the Z80 clock can come from the CPLD so that CPLD can synchronise CPU and VDC access to the SRAM so there is no need for expensive dual port RAM. This will cost a small number of instruction cycles but meets cost targets.

        I am aiming for a low chip count and hence my suggestion of CPLD because the PCB real estate can quickly get expensive especially with 0.1″ chips and spacings.

        The 5 Volt requirement comes from the choice of a Z80. After all this is supposed to be a ‘retro’ style computer. With most micro-controllers today being RISC then it would be nice to have more CISC in amongst the mix.

        I have seen many 680x (Brian has made a couple here) and ‘some’ Z80 style retro SBC’s the limiting factor is most often the video output. Many go for PAL/NTSC so they can use old chips that are still available but in short supply. Some choose to use a cheep RISC micro-controller and end up with very low resolution. The Propeller (160Mips from memory) has been used in Z80 style SBC’s before. I have even seen a Z80 emulator that runs on one COG of the Propeller.

        While the Propeller is a great chip, it is not at all a beginners chip. Even the concept of running 8 CPU’s and time sharing package pins and RAM is a stumbling block for most.

        I am hoping to avoid the Propeller and other complex solutions.

        What I am finding so far with CPLD’s, is that you don’t get much bang for buck in anything that can work with 5 Volts.

        If I can simplify the Video requirements a little and get down to 128 Macro cells then this –
        http://www.digikey.com/product-search/en?wt.z_cid=ref_hearst_0211_buynow&site=us&mpart=ATF1508AS-10JU84&v=313
        might me the answer.

        Perhaps I can just us one big wide level translator around the CPU and go with LVTTL CPLD lol.

        Any suggestions are appreciated.

        I am hoping the end BOM will be something like this –
        Z80 CPU – 20MHz
        128 KByte to 512 KByte SRAM chip(s).
        27Cxx(x) EEPROM or FLASH
        CPLD
        Power socket
        VGA socket
        PS2 (or USB) keyboard / mouse sockets
        Stereo out socket
        Joystick socket(s)
        SD Card socket

        For USB keyboard mouse (probably version 2) I might use a Atmel micro-controller in which case it could also load the boot strap to the CPU (Via the CPLD) so that system boots to SD. Then I wouldn’t need any 27Cxx(c), just has a cheep serial flash chip hanging off the micro-controller.

      • Jonam says:

        You can get a Z180 which runs at 20MHz at 3.3v (or 33MHz @ 5v) and match it to Zilog’s latest eZ8 microcontroller Z8f6081 which has 60Kb flash, a whole bunch of nice peripherals and USB support. Some glue logic and RAM should meet most of your requirements.

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