Adding IceZero To The Raspberry Pi

[Kevinhub] noticed there were quite a few FPGA hats for the Raspberry Pi. Instead going out and buying one of these boards like a filthy commoner, he decided to spin up his own FPGA Pi accessory. This IceZero FPGA board combines the best features from other FPiGA boards, and does it in a form factor that fits right on top of the minuscule Pi Zero.

If you think slapping a Lattice FPGA onto a Pi has been done before, you’re right. Here’s a hat for the Pi using an iCE5LP4K-SG48, an FPGA with 3520 LUTs. The CAT Board from Xess has a slightly bigger FPGA with 7680 logic cells, and the FleaOhm has a monster FPGA on board that costs about $70 USD.

[Kevin]’s IceZero is at the lower end of these Raspberry Pi FPGA hats, using a Lattice ICE40HX4K. That’s only 3520 logic cells, but it only costs about $7 USD in quantity one. The board design is a standard two layer board that shouldn’t be too terrible for hand soldering. The boards are shared on OSH Park, should you want to test this little guy out.

This Pi Hat is specifically designed to be used with Project IceStorm, the Open toolchain for Lattice’s iCE40 FPGAs. That means there’s already a few projects out in the wild that can be easily ported to this platform, and already [Kevin] has a logic SUMP example going on his board.

23 thoughts on “Adding IceZero To The Raspberry Pi

      1. Curves are weird in modern PCB design. You usually stick with either regular angles or circular arcs.

        It’s not a bad PCB in my opinion, and PCB layout is what I do for a living. It’s just odd, and ugly by some people’s tastes.

    1. I don’t understand. I’ve seen a lot of boards and I’m genuinely impressed by this layout. Very compact — able to fit complicated components onto two layers. Pin and part labels, as well as logo graphics. Thoughtful use of thermals to connect to the ground pour. Traces are short and limited crossovers. Pseudo-chassis ground ring.

  1. Well the board works, however…….

    If you look at any line drawing from an artist and from an “artist”, you’ll see how the lines are strait and don’t wonder all over the place. If speed were an issue with this board, the CAD software (good software) would have calculated the impedance of the traces and would have matched the lengths of the lines to keep the timing skew aligned. A two layer board is out of line with this type of board. Four layer with a proper ground plane …..

    Well, the board works.

  2. Ha. I will never understand the Internet-Trolls and critics on Hackaday. The IceZero PCB layout is 2 layers for cost reason only. I can design 4-layer PCBs, it is much much much easier, better signal integrity, but you pay for it in the end. Total BOM including assembly goal for IceZero is $15. I am actually very pleased with this design. This is completely hand drawn using CopperConnection, a truly awesome Gerber drawing tool. No, the PMOD connectors are not impedance controlled for 50ohms and are not trace length matched to within 100ps of skew of each other, but we’re talking PMODs connectors to a Lattice FPGA for expletive sake . PMODs are for like bit-banging SPI shit at 40 MHz and below. IceZero is all about low cost. Volume pricing for 2-layer PCB 1″x2″ is like $1. I challenge anyone out there to design a PCB with 3 power rails ( 1.2V, 3.3V for FPGA+SRAM, 3.3V for PMODs ) and a fairly solid ground plane in only 2-layers. I started with 4, and realized I could do it in 2 without any sacrifices ( other than my time, which is free ). Did I mention, this is open-source and completely free? Sheesh. Give a guy a little respect.

    1. I happen to like the quasi-retro hand-drawn look of the board. I design 16 layer circuit boards and I think this layout is wonderfully efficient and suits the application and requirements wonderfully.

    2. My apologies… I honestly didn’t mean to come off as insulting as I did, and I wasn’t trying to troll.

      Your design is not bad, and upon looking at your site it’s clear you know what your’re doing. This is a very cool board, I love the idea, and I may look into making one as I’ve been meaning to play around with SUMP.

      That being said, I still can’t say I like the “awkward” traces in parts of the design. Just seeing the board in the picture obviously caused me to assume negative things – whether or not they were true. I think the layout could be improved to straighten up these traces, if nothing but for aesthetic – likely still with two layers. These traces would be a problem in a higher speed design – for those new to PCB design wondering why we’re having this discussion. I don’t have experience with CopperConnection, but I also never use an autorouter unless impedance matching shenanigans need to be done. I also agree with other posts that four layer should probably be used at this point; I understand the cost issue, but it’s really not much more for 4 layer these days. Your project has a ton of potential… just giving you some thoughts for future improvements.

      1. Thank you. I am still unclear as to what is so “awkward”. I placed 0.100″ connectors everywhere ( which consume both layers and are absolutely huge, but my target audience loves them ) and then manually routed around them the best that I could. I foresee no signal integrity issues for the intended purpose of this board. I design 3.125 Gbps SERDES circuits for a living, this design is clearly not that.

        1. Its OCD, lines are not perfectly perpendicular so his lizard brain freaked out. It could be worse, there are people actually arguing all trace turns should be rounded or electrons might fall out ;)

          Speaking of serdes, would it be possible to cram basic CSI-2 Transmitter into ICE40HX4K? There is an open source driver for Pee Mipi CSI port (dma raw incoming data right into memory buffer). This means your board could be the cheapest and fastest way of pumping raw bytes into the Pee. I looked up ICE40 and they are rated at 500MHz max IO. Original Pee camera operates around 1GBit/s data stream at 1920x1080x16x30, 2 mipi lanes, 500Mbits per lane. Its only a question of is it possible to fit basic serializer in 3.5K LEs.

          Why? because there is no way to pump more than 40MB/s into Pee right now(taking 100% of usb bandwidth = no network), with Mipi its theoretically possible to go up to 100MB/s (200MB/s on compute module with 4 mipi lanes). 1GBit/s is enough for actually reasonable oscilloscope for example.

          1. Btw Lattice officially markets ICE40 for MIPI bridges, and even offers free mipi-2-parallel IP block for Machxo2 series, so its not all that unreasonable to expect this to be possible.

            example http://www.latticesemi.com/Products/DesignSoftwareAndIP/IntellectualProperty/ReferenceDesigns/ReferenceDesign04/SonySubLVDStoMIPICSI2SensorBridge.aspx

            sadly their official support matrix omits ice40 :(
            http://www.latticesemi.com/en/Solutions/SolutionCategories/MIPIInterfaces.aspx
            but the machxo2 requirements are really small, so maybe its possible to adapt this code into ice40

          2. I’ve found the Lattice ICE devices rather slow compared to what I am used to working with. For a project like HDMI video, I would highly recommend going with a Xilinx Spartan6 for fabric resources, fabric performance and also IO capabilities. I’ve considered doing a Spartan-6-SLX9 version of IceZero, but the fact that only ISE targets it and ISE is a dead tool now is a huge detractor.

  3. Well Brian Benchoff, it looks as you can add another tool to your make a PCB in every available package series of articles – CopperPour. I’ve just seen their video and it looks useful for a project in which you just have to quickly hack something together – and it’s FREE :D

  4. I like the design, seems very well thought out especially considering the constraints; cheap and small.
    Might build one as my Rpi0 is collecting dust and this seems like a good excuse to play with it again,
    thanks for the design!

  5. I forgot to mention a very important feature of the IceZero. With the included GPIO sub-module of the sample design, IceZero may be used as a generic port expander and PWM servo controller for any RaspPi. No Verilog FPGA design experience is required to use these functions. Just download the sample design PROM file into the IceZero. I have sample python for configuring the 24 PMOD signals as generic inputs, outputs and PWM controls for things like reading switching, driving LEDs, servos, etc.

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