Recreating the Commodore PET with an FPGA


[Thomas’] love affair with Commodore computers spans well over 30 years, and not too long ago he decided to recreate one of his favorite Commodore offerings, the PET. As we have seen with similar undertakings, this sort of project is no easy task, but [Thomas] seems to be making his way along nicely.

Using a Xilinx Spartan-6 FPGA on the Digilent Nexys3 dev board, he has implemented the Pet in Verilog. Like the original, his clone contains 16K of both ROM and RAM, utilizing the same simulated 6502 microprocessor he used on a previous Apple ][+ project. The FPGA version of the computer sports a 640×400 resolution which is twice that of the original, so [Thomas] simply doubled the size of each of the PET’s pixels to fill in the extra space.

[Thomas] has made some great progress so far, including the ability to load games and other programs from cassette images over a serial connection. He says that there are still a few loose ends to tie up, but it all looks good from here!

Continue reading to see a short video of Space Invaders running on he PET recreation.

18 thoughts on “Recreating the Commodore PET with an FPGA

  1. It’s not doubled, it’s quadrupled. If you double vertical (200->400), as well as horizontal resolution (320->640), you get 4 times the area, 64000 pixels vs. 256000 pixels. Therefore, each pixel is quadrupled. Doubling pixels would require either stretching 2:1, or pixel sharing, which makes very blurry pictures…

    Cool project, though.

  2. The original PET had 8K of memory (or 4K if you had a REALLY early model), not 16K.

    This is really cool, though!

    If he would make this available as a kit, I’d buy one. I guess he’s looking for a way to re-create the chiclet keyboard ;-)

  3. Jac, I had a math teacher that spent an enourmous amount of money to bump his PET up to 16 K. We got to see all that RAM whenever the computer had to be moved. The motherboard would torque slightly when it was picked up and all the socketed chips would have to be pressed down before it would boot again.

  4. I would love to see someone make a super Commodore 128. Replace the 8502 with a 65816 but a fast one and replace the Z80 with a HD64180 or eZ80 along with better graphics and sound.
    Just to see where the 8 bit world might have gone.

    1. There was a C=65 along the lines of the Apple IIgs but upper management canceled it because they wanted to concentrate on the Amiga.

      The C=128 was very expensive and behind schedule because management insisted on the frankenstein inclusion of a Z80 and an incompatible video chip which required a special monitor with manual switching between modes and crippled performance in both modes. In the end, it cost CBM more to make a C128, 1571 and REU then it did to make an Amiga 500 yet it had only a fraction of the performance.

      Such foolishness is along the lines of making the Vic20 incompatible from the PET and then the C64 incompatible with both. There was also other pointlessly incompatible machines like the +4.

      Compare that to Apple or Atari which maintained 8 bit forward compatibility for their entire 8 bit run.

    1. Hi!

      The SID was really recreated in FPGA. I included it in the newer releases of the 1541 Ultimate. It includes the filters and combined as well.

      Actually, recently I recreated the whole C64, including the VIC-II chip with reasonable accuracy in a Spartan-6 FPGA. This implementation runs demos like Deus Ex Machina quite well!

    2. I think I’d need to post some pictures of the tiny Spartan-6 board that I made which runs the complete C64 (including SID with filters) including the 1541 drive. This board currently outputs analog PAL, but has a HDMI port as well. This HDMI port is currently only used to display the floppy selection menu, but as soon as the upscaling logic is ready (low priority), the C64 output will move to HDMI as well.

  5. 9a3eedi there are projects that have tried to recrate the SID. I can’t find them right now but one thing is the SID had analog filters and these can’t be implemented on an FPGA.

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