Xilinx recently announced the Virtex UltraScale+ VU19P FPGA. Of course, FPGA companies announce new chips every day. The reason this one caught our attention is the size of it: nearly 9 million logic cells and 35 billion transistors on a chip! If that’s not enough there is also over 2,000 user I/Os including transceivers that can move around 4.5 Tb/s back and forth.
To put things in perspective, the previous record holder — the Virtex Ultrascale 440 — has 5.5 million logic cells and an old-fashioned Spartan 3 topped out at about 50,000 cells — the new chip has about 180 times that capacity. For the record, I’ve built entire 32-bit CPUs on smaller Spartans.
That led us to wonder? Who’s buying these things? When I first heard about it I guessed that the price would be astronomical, partly due to expense but also partly because the market for these has to be pretty small. The previous biggest Xilinx part is listed on DigKey who pegs the Ultrascale 440 (an XCVU440-2FLGA2892E) at a cost of $55,000 as a non-stocked item. Remember, that chip has just over half the logic cells of the VU19P.
When the only tool you have is a hammer, all problems look like nails. And if your goal is to emulate the behavior of an FPGA but your only tools are FPGAs, then your nail-and-hammer issue starts getting a little bit interesting. That’s at least what a group of students at Cornell recently found when learning about the Xilinx FPGA used by a researcher in the 1990s by programming its functionality into another FPGA.
Using outdated hardware to recreate a technical paper from decades ago might be possible, but an easier solution was simply to emulate the Xilinx in a more modern FPGA, the Cyclone V FPGA from Terasic. This allows much easier manipulation of I/O as well as reducing the hassle required to reprogram the device. Once all of that was set up, it was much simpler to perform the desired task originally set up in that 90s paper: using evolutionary algorithms to discriminate between different inputs.
While we will leave the investigation into the algorithms and the I/O used in this project as an academic exercise for the reader, this does serve as a good reminder that we don’t always have to have the exact hardware on hand to get the job done. Old computers can be duplicated on less expensive, more modern equipment, and of course video games from days of yore are a snap to play on other hardware now too.
If you’re reading this article on a desktop or laptop computer, you’re probably staring at millions of pixels on a TFT LCD display. TFT became a dominant technology due to its picture quality and fast response times, but it’s not the only way to build an LCD. There are cheaper technologies, such as STN and its color variant, CSTN. They’re rarely used nowadays, but [Wenting Zhang] had one lying around and wanted to take a crack at driving it.
The screen in question came courtesy of a 20th century laptop. It’s a Hitachi SX21V001-Z4, with a resolution of 640×480 pixels. Driver boards for CSTN screens were once readily available, however now such things are difficult to come by.
[Wenting] instead grabbed an FPGA and got to work. Driving displays can be taxing for small microcontrollers, so an FPGA is always a great choice when working on such projects. They’re easily capable of generating whatever weird and wacky signals are required, and can generate many such signals in parallel without breaking a sweat.
[Wenting] successfully got the screen up and running, and hooked up to a VGA input. Image quality is surprisingly passable for still images, though things absolutely go to pieces when motion is introduced. [Wenting]’s demo shows off the screen playing Breath of the Wild, and it’s a great showcase of how far technology has come since the mid-90s.
Driving strange LCDs is a hacker rite of passage, and we see plenty of efforts around these parts. Video after the break.
Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You can see a video of the results, below.
The FPGA board is a ZestSC1 that has a relatively old Xilinx Spartan 3 chip onboard. Still, it is plenty powerful enough for a task like this.
[Tom] has one of the earlier Pano Logic clients, with VGA output and a Xilinx Spartan-3E 1600 FPGA under the hood. Due to limited RAM in the FPGA, and wanting to avoid coding a custom DRAM controller for the memory on the board, there just wasn’t room for a framebuffer. Instead, it was decided that the raytracer would instead “race the beam” – calculating each pixel on the fly, beating the monitor’s refresh rate.
This approach means that resource management is key, and [Tom] notes that even seemingly minor changes to the raytracing environment require inordinately large increases in calculation. Simply adding a shadow and directional light increased core logic utilisation from 66% to 92%!
While the project may not be scalable, [Tom] was able to implement the classic reflective sphere, which bounces upon a checkered plane and even added some camera motion to liven things up through an onboard CPU core. It’s a real nuts-and-bolts walkthrough of how to work with limited resources on an FPGA platform. Code is available on Github if you fancy taking a further peek under the hood.
We reported earlier about Xilinx offering free-to-use ARM Cortex M1 and M3 cores. [Adam Taylor] posted his experiences getting things working and there’s also a video done by [Geek Til It Hertz] based on the material that you can see in the second video, below.
The post covers using the Arty A35T or Arty S50 FPGA boards (based on Artix FPGAs) and the Xilinx Vivado software. Although Vivado will allow you to do conventional FPGA development, it also can work to compose function blocks to produce CPUs and that’s really what’s going on here.
In the over three decades since [Sophie Wilson] created the first ARM processor design for the Acorn Archimedes home computer, the architecture has been managed commercially such that it has become one of the most widely adopted on the planet. From tiny embedded microcontrollers in domestic appliances to super-powerful 64-bit multi-core behemoths in high-end mobile phones, it’s certain you’ll own quite a few ARM processors even if you don’t realise it. Yet none of those processors will have been made by ARM, instead the Cambridge-based company will have licenced the intellectual property of their cores to another semiconductor company who will manufacture the device around it to their specification. ARM core licences cost telephone-number sums, so unless you are a well-financed semiconductor company, until now you probably need not apply.
You will still have to shell out the dough to get your hands on a core for powerful chips like those smartphone behemoths, but if your tastes are more modest and run only to a Cortex M1 or M3 you might be in luck. For developers on Xilinx FPGAs they have extended the offer of those two processor cores at zero cost through their DesignStart Programme.
It’s free-as-in-beer rather than something that will please open-source enthusiasts, But it’s certainly a fascinating development for experimenters who want to take ARM for a spin on their own gate array. Speculation is swirling that this is a response to RISC-V, but we suspect it may be more of a partial lifting of the skirts to entice newbie developers such as students or postgraduates. If you arrive in the world of work already used to working with ARM IP at the FPGA level then you are more likely to be on their side of the fence when those telephone-number deals come up.