Intel Buys Altera For $16.7 Billion

Intel, CPU manufacturer we all know and love, will buy Altera, makers of fine FPGAs, for $16.7 Billion.

While most of the news about this deal focuses on the future of FPGAs in the datacenter, getting Altera IP into Intel fab houses is equally interesting. Intel is the current king of putting transistors on a piece of silicon, and Intel’s ability to put a massive amount of transistors on a chip means FPGAs will become even more capable – more gates, more blocks, and more memory. The most capable Altera FPGAs are being made with a 28nm process; Intel could theoretically double the number of gates with the 14nm process used on the new Broadwell CPUs. There is most likely someone at Xilinx tearing their hair out right now, chain-smoking next to a pot of coffee.

News of this buy out comes about a week after Avago bought Broadcom in the biggest semiconductor deal ever, and a few months after NXP and Freescale merged. Cash Rules Everything Around Semiconductors, it seems.

45 thoughts on “Intel Buys Altera For $16.7 Billion

  1. Hmm nice! Definitely will be interesting to see how this plays out in the marketplace.

    Is going from 28nm to 14nm going to quadruple or double the number of transistors?

    1. Monopoly seldomly ends up ‘nice’, except for the very few, but even they will in the end lose to ‘the other’ monopoly, until there is only one, but then they stop trying and everybody still loses.

    1. Same here. We have had some fantastic progress in FPGA because there has been strong competition and a level playing field. And now, Intel ‘v’ Xilinx seem very one sided.

    2. Intel’s R&D budget is bigger than AMD’s gross income. Interesting things could come from this, though Altera already uses Intel fab (which is built with AMAT gear which uses AE which uses Sekidenko, etc, etc.)

      1. Interestingly enough I hear intel for their upcoming platform also is going for NVRAM, seems there has been some sort of leap in that area to make that possible I figure.
        I hear some tech-sites talk about it initially being NAND -but come-on, that seems highly unlikely, it’s just not usable as real RAM, even if you got it fast enough it would die in a week from the many write cycles.
        It must be one of those new things they have been talking about for years as being just around the corner and having all those lovely superior features, except for real this time.

        1. You use NAND to back actual RAM. Then at power failure you quickly steam the RAM into the FLASH very efficiently. At power on you do the reverse to restore.

          This uses the best if both technologies and may need a small cap the DIMM to allow the operation to complete at unexpected power down.

    3. You mean you’re not the only one fearing that this might mean the slow-choke of FPGAs and ASICs by making everyone go through whatever crippled system of toolchains they can come up with to lock people in? Or is it just the extra paranoia that comes with knowing that any FPGA can now have a backdoor programed into it in a small section of the chip (microcontroller section) and no one would be able to program it out due to being already masked in?

  2. Benefits I see:
    1. More advanced high end parts
    2. (possibly) cost reduced parts on newer processes

    Downsides that’ll probably happen:
    1. Axeing smaller lines like low end Cyclones, Max
    2. Shoehorning crappy Atoms onto FPGAs forgoing ARM
    3. Being vulnerable to Intel’s ADHD and inconsistent “outreach” efforts

    Intel is great at making CPUs, but universally bad at entering any other market. Hopefully they let Altera continue to operate more or less indepedently, but that only lasts until the first change of heads in management.

    1. Intel investors are used to seeing high profit margins, not sure how well FPGA lower end parts fits into that.

      I don’t want the smaller/leaded parts to disappear. New parts tend to be in BGA unless it it a tiny part even then they take useful features/lower speed grades off it. e.g. SERDES, DDR etc before of speeds.

      To break out a BGA these days require multilayer PCB. I am not talking about 4, but you’ll need 6 or 8 layers just to bring out the pins. That basically means that it is outside of hobby budget to order a proto PCB even if you could design/assemble it.

      1. The board design and fab is not the issue. The really hard part is assembly. You might be able to use a toaster oven to solder it on, but picking it up and placing it requires machine precision. Xilinx will still be there for us, hobbyists and pros alike. If all Intel keeps are the big parts then it will be its only customer and Xilinx and Actel will take the rest of the Market.

      2. It is the cost of getting a 6-8 layers board fab at a hobbyist’s budget that I have an issue. You’ll also better design rules to break out 1mm or finer pitched parts. If money were no object, then you can get the proto populated. Proto PCB places usually have that service available.

        Pretty much means that buying a EVB with BGA parts is starting to look attractive when the fab and assembly is taken into account.

        1. Sorry, this is an incorrect statement as much as I hate BGA’s there IS a VIABLE work around.

          You split your design into 2 boards. 4 layers and 4 layers.

          You make a 7 layer board yourself. Place non conductive full drill holes at the corners AND EPOXY THE STACK TOGETHER.

          Now as to our opinion of the companies to forcing us to do such a thing we can grind our teeth down during our sleep or see if we can come up with a fix.

          Granted, a 7 layer board will NOT handle long term heat exposure unless we use a perfect thermal glue/alignment (and ~.01-.06mm alignment, start making that high speed min mill press bro!), and can support a long cure time BUT it is VIABLE!

          I am about 1 year away from attempting this so leave it be. Perhaps someone with the right gear and machining can pull it off for us. And massive kudos and skulls to them!

          *flourish and bow* This is assuming companies like OSHPark and others will be content with their current margin.

    1. How dare you make sense… you don’t question the incompetence of a product like that.

      With that said, maybe they can also fix some of the glitches with the simulation that keeps it from properly replicating race conditions. Every time I tried to trace a signal while it’s propagating through the circuit, it would give me the wrong values even when I modify the circuit to correct the issue. It’s almost like they don’t want us to reverse engineer any circuit that we have to repair. Wait…

  3. And to think that Intel was in the PLD business a long time ago. They now want back in? I found it very hard to use their parts for anything with a long product life time as they have ADHD – they have a habit of getting out of business areas and not in it for long term other than their core business.

    I don’t know if they are going to ditch parts that are on outsourced fabs. What is going to happen for their lower end products that won’t be using Intel’s bleeding end fabs? What happened to that one startup that was using Intel’s fabs for their FPGA?

  4. >biggest semiconducter deal ever
    >biggest semiconducter
    >semiconducter

    Ya see those red squiggles there, HaD? Ya don’t hit post until all the red squiggles are gone.

  5. ಠ_ಠ Not like this. Not like this.

    There has not been one single company that has been ‘acquired’ in the last 30 years that hasn’t been digested into the acidic juices of red tape.

    Aside from the high end Enterprise and Mainstream Desktop everything Intel has tried has been not even half heartedly followed.

    I think Intel finally became wary of the long term forecasting of themselves vs ARM and MIPS and Nvidia.

    Sadly they are taking away from tinkers and innovators. Snatch up what Altera chips you want now as new generations will be poisoned with Intel explicit microcode.

    *depressing sigh* *Kicks soda vending machine with epic wrath and anger*

    Well I guess I’m okay. still need to get my Hot Air re-flow station, I wanted to make nice little cluster of FPGA’s paired with some Rasp Pi 2’s or Beagle Bone Blks. I’ve been hording/collecting .pdfs, schematics, images and webpages in the event that.well. Something like this would happen.

    I know what I need to achieve but news like this sounds ominous as hell.

    Logi-Bone’s and Logi-Pi’s are still out of stock. I’m not afraid of the task length but I’m worried the work/effort as an independent will be meaningless.

    Well guys, leverage your 401k’s toward AMD or Nvidia or an other ARM partner buying Xilinx (Apple? Google/Motorola?).

    If we are lucky Analog Devices will court Xilinx. And pray for the sweet release if it’s Tee-Eye.

    1. Now you have me thinking of TI DSP “Cells”. FPGA style FIRs and IIRs can be very fast, BUT they use a lot of gates – and they are usually optimised for the filter coefficients. Change a coefficient = Recompile the code.
      Compare that with a setup where you just write a variable to a register, and your design / test cycle gets a lot shorter.

      1. I wish [Bil Herd] {most excellent tuts} – http://hackaday.com/2015/05/28/from-gates-to-fpgas-part-1-basic-logic/

        would really explain “Why” FPGA’s are so evolutionary cool.

        He does talk about the very very definitive foundation level. Say it Bill! Say it! Tell folks that FPGA’s are the electronic equivilant of petri-dish!

        Now if you couple this with a Machine Learning and Genetic Algorithims it doesn’t matter how fast [Ghz/Mhz] these things behave. The fact that you can couple these FPGA’s with standard ASICs to have the system test for the most resilant and hyper evolutionary WORKING algorithim.

        Bypassing any ASIC bugs, CUDA farts and get RAW testable logic without ANY OS level bugs, We get pure math crunching out of these things.

        Xilinx has kinda gotten janky due to Vivado/Gen 7 having the ARM based arch wrapping around the FPGA core.

        RISC-V / LEON 3 / etc / hell even Mil Spec/ Rad Hard instruction sets and so forth. Literally the RAW fpga’s can be ANYTHING you can imagine and even things that haven’t been imagined yet.

        Please check out opencores com (and a ton of other sites)

        TI is talking out of there collective butts if they think that fpga’s AREN’T the natural evolution of having a nano-sized robot remaking a crazy 7400 logic chips being moved as fast as the chip is operating itself.

        (Check out some of the TI forums about the DSP’s, people were mad upset at those idiots taking one of the highest classed DSP’s, meshing it with some lame front end CU and cutting the speed by ~15-25% and obsoleting/EOLing the class of chips that were good). For making logic chips TI isn’t a very logical or rational company at all.

    2. The Edison was supposed to mark a new beginning for Intel with embedded and designer end-users with real company backing. Sparkfun had a deal to give it a shot and pushed pretty hard. I don’t know a single person who bought one and have not seen anything lately about how it is going. Too much important connectivity was missing for the price. I’m sure there was plenty of resistance from behind by the old-timers at Intel. Maybe they won.

      1. @TheRegnirps – This. THIS.

        First it was the Galieo

        Then they showed off the Edison in SD format
        [that was sweet, so sweet the electric imp tried to tried the coat tails.],

        then came the half-still born Edison with fully undocumented pin-outs? Having to pull some sort of data when the company says “oh yeah, ‘we support ya, have fun be inventive with this thing”.

        I mean FTW, to release a chip/full blown module and have indie engineers? US? the community? try to scrounge what the pin-outs are? “Oh thank you kind big conglomerate I’m glad you tasked a POST sales engineer that had to receive multiple authorizations to ask ‘please can we give the community the docs?’.

        And seriously at least with the ESP I can use a hobby knife to chop the antenna if I wanted to. (why do that? maybe to use it to process WiFi signals AFTER I’ve filtered them).

        Oh no, with Edison one can’t even receive support if you’ve modified the external packaging in anyway. I mean why? even? the module alone is $50. MINUS the breakout board. Huh?

        Listen I love Blue Label and Patron as much as the next guy, but seriously nightly parties with that shit and private Exec meetings makes one mentally handicapped during decision making meetings. It’s more about Le Egos.

        I can’t condone Cisco’s (not the only company) elitism but at-least Chambers made a fuss about ‘quit jinxing/toxin-ing our gear on the way out, and to our customers we will give you unlisted and empty storage spaces to store/pick-up your gear.’

        It’s so weird you spend your life fighting “the man”, until you sacrifice all your dignity, honor and soul to become a soul sucking back-stabber to ascend only to end up in a position where you are “the man” and well heaven forbid you don’t want to “rock the boat”.

        Between the main semi companies and fork-lift up-graders you would not even imagine the Game Of Thrones being played out.

        And thanks to JIT manufacturing/processing/inventory it’s next-to-impossible to get a cheap stream without signing a contract that promises that you’ll tie your arteries to the chip makers blood stream all the while swearing you’ll never look at another semi company.

        The “Intel Management Platform”, “TPM”, and “VX-T” make me really wary of what do they think they are doing.

        -=-=-=-
        Obligatory, future bow down, sorry Intel please don’t harm my system, I was attempting to give constructive criticism before.
        _____

        “When crappy locks are constructed, installed, no one mentions them and you have them embedded into your home, them you will become hateful toward creeps jingling keys. The only question is how to get rid of their bodies.”

  6. Not sure this bodes well for Altera’s existing customers.

    Intel typically gives “small” customers lousy pricing & support. ie: anyone who only buys a a few thousand CPU’s a year). Altera gives great support to anyone with similar volumes, and that -will- change. Oh, you’re not Google or Microsoft? We’ll let you know next week/month sometime on your “urgent” question, buh-by.

    Intel will almost certainly combine the support (FAE) groups to thin the herd. From a CEO’s standpoint they’re all equal good. Don’t need so many. Reduce headcount. Profit!

    They will combine the sales groups. The markets are different, but they’ll only be salivating on the chance to get Google/Microsoft to buy cpu/fpga hybrids. Profit!

    The Altera layout group (the guys who do the low level ASIC mask design) will probably be let go. After all, Intel already has an awesome group right? Different technology, no experience in the layout issues, but Profit!

    The engineer people will almost certainly be thinned out also? After all, Intel already has an awesome group right? No experience in fpga design, but Profit.

    I think Xilinx will gain quite a few customers, and Altera’s board & big investors are cashing out nicely. Everyone else, phfft….

  7. Haven’t used Altera for years. I have never been able to find anything comparable to the Spartan 3E 500/1200 or Spartan 6-SLX9 range LQFP/256BGA at a similar price. Possibly just not understanding Altera devices though.

    1. Their ranges are pretty comparable. The Cyclone IV EP4CE10 is about equal in price and capability to the Spartan 6-SLX9 for example, and the programmers are much cheaper. The new MAX10 series are pretty cheap also (2K LEs for less than £5 in low volume).

  8. As a former intern at Xilinx, I’m not too worried. It will take Intel a long time to operate at the same level of efficiency/quality as Xilinx, and in the mean time most of Xilinx’s customers will be loyal – if not, it will cost them more. Look at the errata of Xilinx vs Altera.

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