A Complex Programmable Logic Device (CPLD) is a great piece of hardware to have in your repertoire. As its name implies, you can program these chips to serve the logic functions you need. This might be replacing an obsolete chip, or maybe just a way to learn and try different techniques. What better way to learn than to get your hands on a CPLD and give it a try?
I created a CPLD module with the intent of being able to plug it into lots of things including solderless breadboards, but I screwed up. It seems that the plugin space available on a solderless breadboard is 1.1”, I had made the footprint 1” wide leaving no room for a row of wires on both sides. Duh.
But let me back up and show more about what I’m doing , I wanted to make a programmable piece of logic that could be built as a kit one could easily solder at home, could be programmed in-circuit, and could work at 3.3 or 5 volts.
To implement an easily solderable kit I went with an older CPLD part that also has 3.3v and 5v versions that will maintain its programming regardless of power. The logic itself is a CPLD IC from the Altera Max family with two versions that fit the board with either 32 or 64 macrocells. A macrocell is the basic logic building block and it is programmed with logic “terms” and then interconnected to other macrocells through a programmable interconnect.
The CPLD: A surface mount part that fits a through-hole socket
This part known as the EPM7032 and EPM7064, comes in a 44 pin Plastic Leaded Chip Carrier (PLCC) or sometimes called J Lead due to the J shape of the pin leads. This package can be inserted in a through-hole socket or directly soldered to the PCB.
The on-board oscillator is included so that the CPLD can do things statefully and create fast counters on its own without the need for an external clock. If an external clock is available, the higher speed clock on the module can be used to create a clock event on each rising or falling edge of the external clock and still abide by the guidelines for CPLD/FPGA’s that says that you really should use the internal global clock network and not drive a clock input “asynchronously”. This oscillator is rated for a supply voltage between 1.8 and 5.5 volts.
If you watch the video you will see me discuss my personal preference for how I treat the enable “INH” pin on an oscillator; simply put I tend to leave it floating after I check with the spec sheet that doing so is legal.
The kind of reasons that flit through my mind when dealing with this sort of function include the fact that I don’t like to tie an input pin directly to a power rail if I can help it. I.E. I prefer to use a series resistor that would limit current during transients, even if it is not supposed to be needed.
Over the years I have seen problems in production (mass quantities) where occasionally something like power cycling will allow a pin tied directly to a power rail to have a higher voltage than the chip itself which is bad. Lastly with a pin tied to a power rail through a resister, whether power or ground, one can change their mind later and use the pin. This is especially true in my experience for unused gates, which as you probably know should never be left floating or unconnected. By using a pull-up you have a point where you can connect a signal and use the gate without having to cut copper traces.
Programming the CPLD
The 10 pin connector and a handful of resistors comprise the programming circuit. If all of the resistors were pull-ups I would use a resistor network but alas, one is to ground.
To program a standalone CPLD like this, a dedicated programmer is needed. That’s easy for me to say as I usually have several lying around, but if you don’t have one it’s not too painful to get into the game. An approved “Altera USB Blaster” costs $50 and is available from places like Digikey. I have several clones that I got off of Ebay including one that is a clone that supports Altera, Xilinx and Lattice all in one. There is a project and code available on the Internet for making your own clone and I have it on my list of possible videos to do a project of making a programmer clone. I will also be showing a shield design where the main board, Arduino, PIC, etc., can do the programming
The software needed to compile and program the CPLD is available for free from Altera though the older version 9.1 is needed for this older part. The good news is that it’s my favorite older version that had an intuitive timing analyzer which was removed in later versions.
The PCB is a simple two sided design and I tend to do a copper pour for ground and sometimes power as long as the board lends itself to it. Sometimes the pour gets so broken up that it may actually induce issues or just be sloppy in the end result, so again a copper pour is a tool but needs to be managed.
The 3D View
Many if not most CAD packages these days include a 3D view of the end product, though the accuracy of the image it is only as accurate as the 3D models used to represent the parts. Here it can seen where I select 3D model for the 44 pin socket, the programming connector and the oscillator. Here are some of the 3D packages I like to use:
Also many companies have their 3D models for their components. Molex is just one example of a company that does rather well with this.
The mistakes I made don’t affect the function so much as aesthetics, not counting the main issue which is that it doesn’t fit a single solderless breadboard very well.
Once it occurred to me that I might share the design with anyone I was instantly unhappy with the schematic symbol for the CPLD and for the pinout of the 40 pin connector that is its overall footprint. I had grabbed a 40 pin dual row connector symbol and adapted it to a 1” footprint, however instead of the pins numbering 1,2,3,4… down the side like a DIP package it is numbered 1,3,5,7… like a ribbon cable connector. Consequently it’s a non-intuitive footprint for figuring how to connect to the module and for troubleshooting.
Likewise the CPLD pinout is a bit confusing, I used a set of utilities that rely on Boundary Scan Description Language (BSDL) to create the symbol. Most of the big vendors have BSDL files available for their mainstream parts and these allow you to create symbols and footprints (semi)automatically. Like any piece of automation it needs to be treated like a tool and may need further massaging for best results. In this case I let it list the pins alphabetically which is almost random when it comes to tracing a pin on the board. Lets just say I was in a hurry that day.
You pay for those shortcuts at some point down the road. When I go to revise this module I will be sure and give it a pin placement that matches the part itself so that knowing where to put your scope probe is as easy as glancing at the schematic symbol.
There are other improvements that are mostly aesthetic or usefule when working with the board. The pin 1 indicator needs to be more prevalent for several packages and I always like an easy ground point for attaching scope grounds or VOM leads. I will probably add this by adding a two pin connector so that power and ground can be applied directly to the board rather than clipping onto the bottom pins.
Test Before Revise
Before I revise the board I want to make sure that it works in spite of the physical and aesthetic issues. After applying power verifying that the oscillator was working correctly I plugged in the programmer and it sensed the CPLD though the 3.3v version was newer than the programming software and showed up as an “unknown” device.
Next I created a counter in Quartus and assigned pin numbers. A quick compile and download and the counter function as seen by the scope verified that the design was viable.
The quick test circuit in Verilog is pretty simple. The code is listed below and you can download A ZIP file containing both schematic and Verilog test circuits as Quartus II Projects (Requires Version 9.1).
module block1 ( clock, IO11, IO12, IO14, IO16, IO17, IO18, IO19, IO20 );
input clock; output IO11; output IO12; output IO14; output IO16; output IO17; output IO18; output IO19; output IO20; reg [15:0] q;
assign IO11 = q; assign IO12 = q; assign IO14 = q; assign IO16 = q; assign IO17 = q; assign IO18 = q; assign IO19 = q; assign IO20 = q;
always @ (posedge clock) begin q <= q + 1; end
Where to go from here
As I mentioned I will be doing a second revision of the board paying more attention to the details needed when sharing a design or doing any amount of troubleshooting. Since I need to make the width of the bottom connector .9” or less I may go ahead and make it .6” which is a standard “wide” DIP footprint. Doing so will mean having the underside pins protrude through the CPLD socket footprint. I would not do this in a production situation as it is hand assembly at that point, but then one of the goals was to make a hand solderable kit. The compromise for hand soldering is that the oscillator really needs to be in an SMD surface mount case, the through-hole versions are huge and don’t typically support the voltage range I wanted.
Also I really like surface mount LEDs, I think they look cool.