HiFive1: RISC-V In An Arduino Form Factor

The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.

Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding campaign on CrowdSupply. It’s a RISC-V microcontroller, completely open source, and packaged in the ever so convenient Arduino form factor.

The heart of the HiFive1 is SiFive’s FE310 SoC, a 32-bit RISC-V core running at 320+ MHz. As far as peripherals go, the HiFive1 features 19 digital IO pins, one SPI controller, 9 PWM pins, an external 128Megabit Flash, and five volt IO. Performance-wise, the HiFive1 is significantly faster than the Intel Curie-powered Arduino 101, or the ARM Cortex M0+ powered Arduino Zero. According to the crowdfunding campaign, support for the Arduino IDE is included. A single HiFive1 is available for $59 USD.

Since this is an Open Source chip, you would expect everything about it to be available. SiFive has everything from the SDK to the RTL available on GitHub. This is an impressive development in the ecosystem of Open Hardware, and something we’re going to take a look at when these chips make it out into the world.

29 thoughts on “HiFive1: RISC-V In An Arduino Form Factor

    1. A PCB design developed with only one purpose – to make all breadboards completely useless. It was designed by evil d***heads, and we are stuck with it because every new *uino developer is forced to follow it if he wants to sell his junk…

      1. One of those things where if they’d just taken the small pain of fixing the problem, it would save tons in the future. Like waiting for the Americans to finally understand Metric SI units.

        Still, in the meantime it’s easily fixed with some DuPont connector flying leads. The first problem that is, not the spaceship-crashing one.

    1. Probably just the pin name, since that is the name of the actual pin. Look on the Arduino Uno and you will see the same pin name.

      Open-source RTL will make nice peripherals like UARTS, SPI ports, etc. just fine in standard cells. To make an A/D or D/A converter will mean using process-specific libraries, which kind of goes against “open source.” Licensing would mean that the documentation for the A/D could not be released. Still, it is possible that a chip like this could have an A/D, if the company has the rights to use the IP for it.

      Chips are made using “standard cells” which are basic things like registers, and gates, or gates, etc. You place down horizontal rows of alternating power/ground wires, and the standard cells are designed to simply fit between these wires. This gives you all of your basic logic, and you pretty much need this to make any digital chip.

      To make anything “analog-ish,” including A/D, D/A converters, PLL (clock generators), SERDES, any sort of non-volatile memory, and even dense RAM requires libraries specifically for that purpose. Depending on the fab, you can pay extra for these (sometimes a lot extra). I am guessing that this is why an external FLASH is uses (some processes do not even support FLASH).

    1. Read the campaign, it’s available for $50 for a bare chip.

      And before anyone complains about the price, don’t forget that this is the first RISC-V chip available to the public. The price will go down over time.

    1. 1. Because they’re still rolling them out, and need to finish the campaign to be able to afford the chips themselves (they don’t just have 10,000 of them lying around I bet).
      2. Because datasheets don’t come magically attached to the chip itself, with every detail you could ever need to know. Someone has to actually write and revise those dreadfully long, detailed documents, you know?

  1. I imagine the high cost of the chip is due to the cost of the Mask used to make these ASICs.That alone can cost anywhere between $2-7Million. This should change though, especially if semiconductor companies get behind this chip the same way that IBM & Intel got behind Linux. They get access to a very performant CPU core with a premade SDK and unlike the ARM cores, they don’t have to pay anyone royalties.

    Very interesting. I really like where this is going. SO much so that I might consider to pre-order a board from crowd supply despite the cost.

    1. IIRC they’re using an old process (180nm IIRC) to fab these. The mask costs should be significantly lower than that!

      IIARC in later runs they want to get the board cost down to $39.

      The big shame with this 320MHz microcontroller is the lack of memory – a 16KB data scratchpad is not a lot to play with.

  2. Awesome. It is a good start. However, two UARTs two,QSPIs, two 4 channel PWM, and a single timer is all peripheral it’s got, I am surprised that there is even no I2C, no ADC.

    If it has a significant lack of peripheral there is no real point of having this high performance like 320MHz. I hope they would focus on peripheral next time.

  3. I’ve managed to get one of these for Christmas, the Founder’s Edition – the hint to my wife worked, For now it seems to work as advertised.

    Last night I built a Ubuntu VM under VirtualBox, pulled the Github repos, built the tool chain from source, complied a “Hello World”, mapped through the FTDI device, and flashed it to the board.

    I might try bit-banging some I2C or WS2812Bs.

    1. Hi Mike,I would be very grateful if you can share with us some real life insights and you findings how fast HiFive1 can bit-bang it’s (GPIO’s) ports or do ring-oscillator loops. (GPIO1->INV->GPIO2->back Inv. GPIO1 loops)
      Thank you in advance.

      1. Hi Jovan,

        I’ll put that on my to-do list :-)

        Apparently from a post on forums.sifive.com the GPIO can work at 1/15th the CPU frequency using atomic operations, or 1/2th the CPU frequency using the PWM module.

        I like that test with the inverters, but won’t be breaking out the iron – I’ll try reading GPIO2, inverting the value and writing it to GPIO1, while the two pins are wired to together.

      2. Hi Jovan,

        On the HiFive1, GPIO1 -> Level shifter -> header -> Jumper Wire -> header -> level shifter -> GPIO0 takes about 125ns (or can be done about 8,000,000 times a second).

        This was timed with a small bit of C code – a 100M lookps of “set GPIO1 to low, wait for GPIO0 to go low, set GPIO1 to hgh, wait for GPIO0 to go high” which takes about 25 seconds to run.

Leave a Reply

Please be kind and respectful to help make the comments section excellent. (Comment Policy)

This site uses Akismet to reduce spam. Learn how your comment data is processed.