[Stephen Edwards] had some time one Christmas. So he took a DE2 FPGA board and using VHDL built a pretty faithful reproduction of an Apple II+ computer. He took advantage of VHDL modules for the 6502 CPU and PS/2 keyboard, and focused more on the video hardware and disk emulation.

According to [Stephen], you can think of the Apple II as a video display that happens to have a computer in it. The master clock is a multiple of the color burst frequency, and the timing was all geared around video generation. [Stephen’s] implementation mimics the timing, although using more modern FPGA-appropriate methods.

The FPGA also has a read-only disk emulator. The image resides on an SD card and an SPI interface loads it into memory as required.

The DE2 board isn’t the cheapest around, although if you are a student you can get a break (in the neighbourhood of $200 instead of $400). They are so frequently used in schools though, that you can often pick one up for a good bit less on the used market. Also, there are plenty of cheaper boards with the same Altera FPGA that should be fairly straightforward enough to use.

[Stephen] notes that the FPGA version takes less power than a real Apple II+ and much less than a PC emulating one, although — as he notes — that’s hardly fair since the PC has a lot of overhead that has nothing to do with the emulation.

Of course, you can emulate the same type of machine on smaller hardware. We’ve even seen one based on an AVR processor.

20 thoughts on “Apple II FPGA

    1. Perhaps, but the DE2 board is still the one we’re using in my uni classes.
      Despite us all learning on DE2, iCEsticks are more popular among the students who decide to buy their own.

  1. Quote: “you can think of the Apple II as a video display that happens to have a computer in it”

    Most of the old computers were like that. With such slow CPU’s they needed that hardware leverage for video so they were essentially a GPU made with 74xx logic and perhaps a CRTC thrown in that synchronized and/or managed the CPU.

    To get anything happening on screen worth looking at they needed the highest ration of pixels changed per CPU write to RAM.

    1. Agreed. Most 6502 computers with video in the late 1970s, early 1980s were carefully designed to take advantage of the fact that the 6502 doesn’t use the databus during the first half of each clock cycle. Since PAL and NTSC both have a line frequency of about 64 microseconds, it makes sense to run the processor at just above or just below 1MHz so that the video can process one character per CPU clock cycle for a 40-character display, or two characters per CPU clock cycle for an 80-character display.

      Depending how you think about it, the Apple 1 was even more of a “Display with a computer attached”, or maybe more like a “Terminal with a computer attached”. Most of the chips were to generate the video signal. The computer part of the Apple 1 was no more than a CPU, a PIA to interface with the keyboard and video via two ports (7 bits per port, a strobe for the keyboard and an acknowledge for the video), and memory.


  2. Time has moved a lot in our favour. $130 (without academic discount) now buys you a DE board with roughly 4 times the resources of the old DE2, plus a couple of ARM cores thrown in for good luck.

      1. This is a DE2, not a DE2-115 (yeah I know, namespace pollution is largely ignored in the world of FPGA boards). It has a Cyclone 2 with about 35000 LE’s. I recently got a pre-owned one and I like it because it has a lot of peripherals.

        But yes I agree with your remark: The DE2 is still quite expensive at almost $500, and there are better, newer boards that are cheaper.

        Those who are interested should also look into FPGAs from other manufacturers: Last year at the Hackaday Superconference I got a Digilent Arty which costs about $100. It doesn’t have much onboard hardware but it does have four 8-GPIO pin headers (for which Digilent sells numerous peripherals) and it has Arduino headers. The Xilinx FPGA on the Arty has about the same amount of logic space as the Altera FPGA on the DE2, but I get the feeling that Xilinx is a little more efficient; the Virtual Propeller project ( takes up less than 10,000 LE on the Xilinx, and more than 14,000 on the DE0-Nano (I’m sure Your Mileage May Vary).


  3. How hard would it be to port this to the MiST FPGA? There is a core for that unit, although it doesn’t appear to be as well rounded as this one. There is a moderate user base for the MiST who could take advantage of this awesome work! There is a growing userbase for the less turnkey MiSTer project, which has a good deal more active core development at this time.

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