FPGA For All — CERN Releases “colibri” VHDL Library

September 24, 2026 by Tyler August 22 Comments

Since you’re reading Hackaday, we’re pretty sure CERN needs no introduction, so we’ll get right to it– they’re giving back again, this time with a VHDL library called “colibri” containing over 100 components, functions, and procedures to help jumpstart your next FPGA project.

Like a lot of what CERN gives away under its CERN Open Hardware Licence, this library and the functions in it were developed in house to make CERN run better– specifically to streamline the development of gateway devices. As you might imagine, with the prodigious amount of data CERN’s various experiments spit out, FPGAs have become a key part of many of them. The best part is that because the fine folks at CERN don’t want to get locked in, everything here is vendor-independent and has been tested on multiple platforms. Speaking of tested, you get self-checking testbenches in there to make sure everything’s working, and there’s even formal verification, at least for some things. We’ve seen formal verification in software compilers, but its not common in the FPGA world. The whole thing is on GitLab if you want to take a look.

While CERN’s library might not have much to help you make a ternary processor or bus controller with everyone’s favourite programmable silicon, much like software libraries you can save some time at least not implementing say, SPI or i2c– both of which are in colibri, along with a whole lot more.

Thanks to [Alberto Perro] for the tip!

Pulse: A New VHDL Simulator

September 14, 2026 by Maya Posch 9 Comments

With VHDL being arguably more deterministic and bullet-proof than Verilog, it’s good to see another open source VHDL simulator joining the fray that is not a variation of ghdl. Written by [Óscar Grimal] in C++ with an MIT license, the Pulse project is a still in progress package that provides the entire toolchain, from the compiler to the requisite waveform output.

This waveform output is provided in the form of a text-based user interface (TUI), which at the very least helps a lot with making it cross-platform compatible. As dependencies only a C++20 capable compiler and CMake are indicated.

Of course, with VHDL being a rather hefty language especially once you start piling up the associated standard library, the currently supported language and library features are somewhat limited still so that you’re limited to basic IEEE packages and types, with default values are not supported yet.

Per the roadmap on the GitHub project’s Readme more VHDL language features including generics and additional types will be added, along with an enhanced simulation engine. It’s also said that mixed-language support with Verilog will be added, though SystemVerilog looks to be getting the short end of the stick as usual.

It will definitely be interesting to compare this package to ghdl.

Commodore 64 On New FPGA

July 28, 2025 by Bryan Cockfield 19 Comments

When it comes to getting retro hardware running again, there are many approaches. On one hand, the easiest path could be to emulate the hardware on something modern, using nothing but software to bring it back to life. On the other, many prefer to restore the original hardware itself and make sure everything is exactly as it was when it was new. A middle way exists, though, thanks to the widespread adoption of FPGAs which allow for programmable hardware emulation and [Jo] has come up with a new implementation of the Commodore 64 by taking this path.

The project is called the VIC64-T9K and is meant as a proof-of-concept that can run the Commodore 64’s VIC-II video chip alongside a 6502 CPU on the inexpensive Tang Nano 9k FPGA. Taking inspiration from the C64_MiSTer project, another FPGA implementation of the C64 based on the DE10-Nano FPGA, it doesn’t implement everything an original Commodore system would have had, but it does provide most of the core hardware needed to run a system. The project supports HDMI video with a custom kernel, and [Jo] has used it to get a few demos running including sprite animations.

Built with a mix of Verilog and VHDL, it was designed as a learning tool for [Jo] to experiment with the retro hardware, and also brings a more affordable FPGA board to the table for Commodore enthusiasts. If you’re in the market for something with more of the original look and feel of the Commodore 64, though, this project uses the original case and keyboard while still using an FPGA recreation for the core of the computer.

Circuit diagram of linear-feedback shift register.

Can We Replace A Program Counter With A Linear-Feedback Shift Register? Yes We Can!

May 31, 2025 by John Elliot V 32 Comments

Today we heard from [Richard James Howe] about his new CPU. This new 16-bit CPU is implemented in VHDL for an FPGA.

The really cool thing about this CPU is that it eschews the typical program counter (PC) and replaces it with a linear-feedback shift register (LFSR). Apparently an LFSR can be implemented in hardware with fewer transistors than are required by an adder.

Usually the program counter in your CPU increments by one, each time indicating the location of the next instruction to fetch and execute. When you replace your program counter with an LFSR it still does the same thing, indicating the next instruction to fetch and execute, but now those instructions are scattered pseudo-randomly throughout your address space!

Continue reading “Can We Replace A Program Counter With A Linear-Feedback Shift Register? Yes We Can!” →

A slide from a talk about Spade language with a diagram about how it fits in with Verilog, VHDL, and HLS.

The Spade Hardware Description Language

April 13, 2025 by John Elliot V 15 Comments

Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden.

Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to define hardware which can be rendered in silicon. Hardware defined in HDLs might look like software, but actually it’s not software, it’s hardware description. This hardware can be realized myriad ways including in an FPGA or with an ASIC.

You have probably heard that your CPU processes instructions in a pipeline. Spade has first-class support for such pipelines. This means that design activities such as re-timing and re-pipelining are much easier than in other HDLs where the designer has to implement these by hand. (Note: backward justification is NP-hard, we’re not sure how Spade supports this, if it does at all. If you know please enlighten us in the comments!)

Spade implements a type system for strong and static typing inspired by the Rust programming language and can do type inference. It supports pattern matching such as you might see in a typical functional programming language. It boasts having user-friendly and helpful error messages and tooling.

Spade is a work in progress so please expect missing features and breaking changes. The documentation is in The Spade Book. If you’re interested you can follow development on GitLab or Discord.

So now that you know about the Spade language, are you planning to take it for a spin? You will find plenty of Verilog/VHDL designs at Hackaday which you could re-implement using Spade, such as an easy one like Breathing LED Done With Raw Logic Synthesized From A Verilog Design (see benchmarks) or a much more challenging one like Game Boy Recreated In Verilog. If you give Spade a go we’d love to see what you come up with!

Continue reading “The Spade Hardware Description Language” →

Did You Know YoSys Knows VHDL Too?

December 4, 2024 by Elliot Williams 8 Comments

We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in Verilog or VHDL, your choice. Very cool!

Verilog and VHDL are kind of like the C and ADA of the FPGA world. Verilog will seem familiar to you if you’re used to writing code for computers. For instance, it will turn integer variables into wires that carry the binary values for you. VHDL code looks odd from a software programmer’s perspective because it’s closer to the hardware and strongly typed: an 8-bit integer isn’t the same as eight wires in VHDL. VHDL is a bigger jump if you have software in your brain, but it’s also a lot closer to describing how the hardware actually works.

We learned Verilog, because it’s what Yosys supported. But thanks to GHDL, a VHDL analyzer and synthesizer, and the yosys-ghdl-plugin, you can write your logic in VHDL too. Does this put an end to the FPGA-language holy wars? Thanks, Yosys.

[Michael] points out that this isn’t really news, because the oss-cad-suite install has been doing this for a while now, but like him, it was news to us, and we thought we’d share it with you all.

Want to get started with FPGAs and the open-source toolchain? Our own [Al Williams] wrote up a nice FPGA Boot Camp series that’ll take you from bits to blinking in no time.

Making USB Blaster Clones Work For Linux

July 29, 2024 by Al Williams 4 Comments

The last time we checked in with [Downtown Doug Brown], he had some cheap Altera USB Blaster clones that didn’t want to work under Linux. The trick at that time was to change the device’s 24 MHz clock to 12 MHz. This month, he’s found some different ones that don’t work, but now the clock change doesn’t work. What’s the problem?

He also picked up a Terasic clone, which does work on Linux and is considered, according to [Doug], the best of the clones. The units were superficially similar. So what follows is a lot of USB tracing and dumping of the CPLD chip’s configuration.

Continue reading “Making USB Blaster Clones Work For Linux” →