Joining The RISC-V Ranks: IBM’s Power ISA To Become Free

IBM’s Power processor architecture is probably best known today as those humongous chips that power everything from massive mainframes and supercomputers to slightly less massive mainframes and servers. Originally developed in the 1980s, Power CPUs have been a reliable presence in the market for decades, forming the backbone of systems like IBM’s RS/6000 and AS/400 and later line of Power series.

Now IBM is making the Power ISA free to use after first opening up access to the ISA with the OpenPower Foundation. Amidst the fully free and open RISC-V ISA making headway into the computing market, and ARM feeling pressured to loosen up its licensing, it seems they figured that it’s best to join the party early. Without much of a threat to its existing business customers who are unlikely to whip up their own Power CPUs in a back office and not get IBM’s support that’s part of the business deal, it seems mostly aimed at increasing Power’s and with it IBM’s foothold in the overall market.

The Power ISA started out as the POWER ISA, before it evolved into the PowerPC ISA, co-developed with Motorola  and Apple and made famous by Apple’s use of the G3 through G5 series of PowerPC CPUs. The PowerPC ISA eventually got turned into today’s Power ISA. As a result it shares many commonalities with both POWER and PowerPC, being its de facto successor.

In addition, IBM is also opening its OpenCAPI accelerator and OpenCAPI Memory Interface variant that will be part of the upcoming Power9′ CPU. These technologies are aimed at reducing the number of interconnections required to link CPUs together, ranging from NVLink, to Infinity Fabric and countless more, not to mention memory, where OMI memory could offer interesting possibilities.

Would you use Power in your projects? Let us know in the comments.

38 thoughts on “Joining The RISC-V Ranks: IBM’s Power ISA To Become Free

    1. I love me some AIX – talk about uptime…. You can even upgrade the kernel in latest releases without a reboot, and boot volume resizing/mirroring/migrations/etc have been no problem for a long time.

  1. The real place you find power architecture… Embedded! Almost every GM vehicle made in the past 15 years. Dodge, Cummins, many Fords. Cisco routers. And that’s just quickly off the top of my head!

  2. >Would you use Power in your projects?
    Considering it is only the ISA that’s ‘free’ and not the actual HDL or RTL implementation. The answer is 99.99% ‘No’ for the HaD readers. It is only a question if you don’t understand what’s being released or asking a different crowd.
    For RISC-V, at east there are some source code floating around as a starting point as well as chips.

    1. In fact, not so small: the synthesis of the “microwatt” core for Spartan-7 resulted in 11k LUTs and 4k FFs. Not bad for the first core, but definitively it does not fit in tiny FPGAs. In the case of RISCV, there are much more options and typical low-end cores fit in only 1k LUTs.

      1. Leaving aside for a second that it’s fairly easy to take any of the existing RISC-V soft cores and “upgrade” them to POWER (replace instruction decoder, add the small bits of missing functionality), POWER does have a practical lower core size, just as RISC-V has a practical upper core size (note I’m talking compatible chips here, not comparing two different RISC-V ISA versions/sets/whatever that would not be able to run the same binaries).

        POWER’s lower practical limit is probably between something like an 8051 and the current prototype soft core. RISC-V plays quite nicely in that space and below it (where POWER can’t reach) and should have a long and bright future there. It’s far too early to tell what will happen in the space above that, and will be exciting to see what emerges!

        1. I think that the lower practical limit depends of the compiler compatibility. In the case of RISCV, the GCC compiler requires only 37 instructions from the RV32I ISA set, which enables produce RISCV cores with around 1k LUTs that are compatible with the GCC and, as result, compatible between them.

          In the case of Power, I am not aware about what is defined as a minimal ISA, but the Power ISA V1 (regarding the POWER1) is mentioned in the Power ISA V3B specification as supporting 144 different instructions, including floating point instructions. As long is possible disable the use of floating point in GCC, the number of different instructions reduces to 113. Unfortunately, the GCC dropped the support for POWER1 years ago, which means that the PowerPC ISA appears to be the current minimal supported Power ISA in the GCC. Although not 100% sure, I guess the PowerPC ISA requires support all the Power ISA V1 and the PowerPC ISA at the same time, which means support a total of 166 instructions, which does not include floating point instructions, since they can be easily removed via a compiler switch.

          Although most of the additional instructions are not really so complex to implement, they require extra logic space when comparing with a typical RV32I core and I guess the minimal 32-bit PowerPC compatible with GCC requires at least 4x more logic (4k LUTs) when compared with a typical RV32I. In the case of Power ISA V1, the complexity is reduced to around 3x (3k LUTs).

          Of course, this is mere speculation from my side… but make a similar analysis in the microwatt and this will make some sense: the decode logic in microwatt appears to support 196 different instructions, which of course does not includes floating point or vector instructions. This means that the instruction decode and execution is at least 5x more complex than the RV32I. Also, as long the microwatt is a 64-bit core, it requires 2x more logic when compared to the RV32I, which result in 10x more complexity, which is confirmed by the Vivado build (around 1k LUTs in a typical RV32I vs. 11k LUTs in the microwatt).

          Anyway, case this theory is correct, 3k LUTs for a 32-bit user-space only POWER1 is not so bad when you think it is a big-endian processor (which means better network performance) and supports multiply/divide instructions without software emulation as in the RV32I… What a time to be alive! :)

          1. My understanding is that the license for the ISA does allow basically any soft core development, distribution etc, so it’d be interesting to put together a real 32-bit minimal POWER1 type soft core and see what’s feasible. Who knows, if there’s demand for one perhaps it could even be proposed and added as a minimal official ISA variant!

          2. I am definitely interested in playing with the microwatt or other small Power core, no commercial projects in mind. GCC support is a big plus.

            Regarding GCC dropping support for POWER1 (and early ARMs), they probably did that due to perceived lack of interest and/or maintainers. If interest were to pick up and potential maintainers started popping up, they might change their minds. It’s only software, easy (technically) to resurrect old code if the political will is there.

  3. “Originally developed in the 1980s, Power CPUs have been a reliable presence in the market for decades, forming the backbone of systems like IBM’s RS/6000 and AS/400 and later line of Power series.”

    Just how different is the one in the mainframes vs what’s offered here? Also with this development maybe the Amiga might have a chance.

  4. “made famous by Apple’s use of the G3 through G5 series of PowerPC CPUs”

    PowerMacs used PowerPC 600 family at first (601, 603, 604, 620, etc), G3 started with the 750 chip (the 3 meaning third gen of the PowerPC chips). First PowerMac 8100, 7100 and 6100 had 601 chips. The transition from 68K to PPC made them famous, no need to wait for 3rd generation for being big news. These chips were also “going” to save Amiga.

    Wikipedia “Timeline of Macintosh models” has a nice list with links. 1994 was the year. G3 appeared 1997.

  5. I wanted to try it on linux on windows:
    At least on my machine it seems not to source the right headers when running make on the microwatt directory. I dowsn’T find getpagetsize and MAP_ANONYMOUS. Using ghdl 0.36 for ubuntu14 (pre-compiled binary from, it aborts the compilation with following error:

    Execution terminated by unhandled exception
    Exception name: STORAGE_ERROR
    Message: stack overflow (or erroneous memory access)
    Call stack traceback locations:
    0x7ff44c5a032e 0x7fffeb0fd803
    ghdl:error: compilation error
    make: *** [fetch2.o] Fehler 1

    file simple_ram_behavioural_helpers.c has an error anyways at line 117, an argument to fprintf is missing, I’d assume that it is __func__ :). No I don’t have a real linux machine to try this on, I’d try on windows with mingw next…

    1. Thanks for trying it out! Some strange issues there – unistd.h should provide getpagesize() and sys/mman.h should provide MAP_ANONYMOUS. The ghdl SEGV is frustrating, I checked and I’m using a newer version of ghdl (included in Fedora 30).

      As you suggest, I am missing an argument to fprintf() – thanks for catching it.

      1. Anton, it’s nice to see that you are providing fixes quickly. I saw a bunch of recent commits. A few questions:

        * Do you have a mailing list or something to communicate with users? or is this your preferred place?

        * Any plans to put microwatt on

        * Any reason I shouldn’t try this on Xilinx Web ISE? I’m a FPGA/VHDL noob but do have a little experience with ISE. Plus I hate doing multi gigabyte downloads on my cheap 3.5 MB internet connection.

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