Yosys Fronts For Xilinx ISE

We always marvel at how open-source tools can often outstrip their commercial counterparts. Yosys, the open-source tool for Verilog synthesis, is a good example. Although the Xilinx ISE design suite is something close to abandonware, a lot of people still use it because it supports older FPGAs the newer tools don’t. Its Verilog parser is somewhat slow to catch up to new standards, and according to a recent GitHub update, Yosys can now provide files for ISE that target Spartan 6, Virtex 7, and Series 7 FPGAs. In addition, there is some support for Spartan 3, Virtex 2, 4, and 5, although those are not ready yet.

According to the post, you’ll want to use the synth_xilinx command along with the -ise option and a -family option that matches your target (that is, xc6s for Spartan 6).  On the output side, you’ll write an EDIF file using the write_edif command.

This is not to say that the Xilinx XST parser that processes Verilog for ISE is terrible. However it does lag behind on some features, and if it doesn’t work… too bad. Xilinx has a lower focus on ISE and its variants in favor of Vivado which doesn’t support many older chips. With Yosys, there’s an active community around the program and, if you must, you can dig in and fix any problems yourself. You can at least use the source code to answer what if questions.

We’ve covered some tools and tricks for Yosys and the Lattice targets. If you are wanting to get started, there’s always our boot camp.

11 thoughts on “Yosys Fronts For Xilinx ISE

  1. If the software requires the user to modify the source code to make it work correctly, then it’s something to be avoided. Seriously the guys who wrote the code to begin with need to take responsibility for their failures instead of fobbing it off on the user community. Most of who are not C gurus.

    1. Yes, because modifying the machine code binary to fix some bug is better right? Because everybody who isn’t a C guru must be an IA32 machine language guru instead.

      I think the words “if you must” apply here. I’ll take the tool that gives me the _option_ to make changes to it if I need to, over the one that’s locked down.

      Change is constant, and I can’t guarantee that the ABI of my operating system will remain 100% compatible with what I am using today, or what I was using 10 years ago. Windows 64-bit already dropped support for 16-bit applications. Microsoft are slowly trying to shed themselves of Internet Explorer. What’s to say your unmodifiable tool is going to keep working into the future?

    2. I don’t understand? Modify what? This is entirely a work in progress and a completely free and transparent one.

      You don’t have to use Yosys. Keep using ISE/Synplify and stop complaining about having more options available to you.

    3. Rant all you want. Xilinx has been ignoring complaints like yours for over a decade and they’re still (sadly) dominating their industry.

      Seriously, back in 2000 or so, one of the two possible professors for Cornell’s computer architecture course chose Xilinx ISE as the tool for students to work with. His rationale:

      “In the real world, you will have to work with poor quality tools. So that you may learn real-world applications, I have chosen the worst toolchain I could find to teach this class.”

      The other professor chose Berkeley CAST, which was weird and esoteric but at least consistent and not really buggy. (It seems to not exist any more after 2 decades?)

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  2. I don’t understand following sentece: “Yosys can now provide files for ISE”.

    Does it mean the free opensource Yosys tool can export it’s data to closed source Xilinx ISE, which is “something close to abandonware”? So i still can’t get away without using that original closed source tool?

    (i’m not b*tching, because i know the opensource developers probably don’t want this to be final state. just want to know what the situation is right now with opensource toolchain for spartan 6…)

    1. Yosys do the synthesis, ISE still do place and route and bitfile generation.
      The good thing is yosys has a better support than ISE, ie SystemVerilog for example, only supported by Vivado.

    2. Based on what I’ve seen from symbiflow so far – I believe that this is a pretty critical step in reverse engineering that last closed-source bit in the toolchain. (e.g. ISE is still needed for PnR and bitfile generation, but replacing synthesis with yosys makes that last bit MUCH easier.)

      For chips still supported by both Vivado and ISE it probably doesn’t mean that much, but for full support of older chips not supported by Vivado I believe this is a major step forward if I’m understanding what I’ve read in Symbiflow’s documentation correctly.

      Symbiflow support for Spartan 2 series chips would be very exciting for some people I work with, because keeping a Windows XP machine around to run ISE 10 is a fscking nightmare. Xilinx still sells the chips to customers but doesn’t offer toolchains for them that run on any modern OS!

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