Slice Your Next FPGA Design

A recent trend has been to convert high-level constructs into FPGA code like Verilog or VHDL. Silice goes the other way: it converts very hardware-specific concepts to Verilog and aims to be a more expressive and easier to use language.

Why Silice? The project’s web page enumerates its design goals:

  • A clean, simple syntax that clearly exposes the flow of operations and where clock cycles are spent.
  • Precise rules regarding flow control (loops, calls) and their clock cycle consumption.
  • Familiar hardware constructs such as always blocks, instantiation, expression tracking (wires).
  • An optional flow-control oriented design style (automatic FSM generation), that naturally integrates within a design: while, break, subroutines.
  • The possibility to easily describe pipelines.
  • Automatically takes care of creating flip-flops for variables, with automatic pruning (e.g. const or bindings).
  • Generic interfaces and grouped IOs for easy reuse and modular designs.
  • Generic circuits that can be instantiated and reused easily.
  • Explicit clock domains and reset signals.
  • Familiar syntax with both C and Verilog inspired elements.
  • Inter-operates with Verilog, allowing to import and reuse existing modules.
  • Powerful LUA-based pre-processor.

There are several examples of the different styles of coding Silice supports, ranging from the obligatory blinking LED example to a RISC-V CPU and a video processing application. Here’s part of the blinking example, just to give you a taste of what it looks like:

algorithm main(output uint5 leds)
intensity less_intense;
uint26 cnt = 0;
leds := cnt[21,5] & {5{less_intense.pwm_bit}};
cnt := cnt + 1;

algorithm intensity(output uint1 pwm_bit)
uint16 ups_and_downs = 16b1110000000000000;
pwm_bit := ups_and_downs[0,1];
ups_and_downs := {ups_and_downs[0,1],ups_and_downs[1,15]};

Of course, the real benefit over straight Verilog is only apparent with some of the more complex examples.

Working on a project using Silice? Drop us a tip so we can share it with everyone. If you really want to get close to the hardware, you can see an FPGA teardown. If you want to compare Slice to another alternative hardware description language, check out SpinalHDL.

12 thoughts on “Slice Your Next FPGA Design

  1. Al, buddy, pal. Excellent coverage… but you have splattered “Slice” everywhere including the tags and the name is “Silice” like the name “Cylus”. We’re going to collectively close our eyes while you make a few corrections.

    1. Regarding “Slice” vs. “Silice”, this is typical of wtat happens when we’re (mis)taught to read and spell as if our written language were logographic*, all but ignoring the sounds of the letters, instead regarding the abstract >>appearance<< of the words. This teaching apparently discourages attention to detail, which explains this consistent mistake. It's plain that the words
      Silice and
      ook similar, but when spoken according to sounds of the letters, they are quite different.
      See the book from roughly six decades ago; [Why Johnny Can't Read], by (iirc) Rudolf Flesch.
      *Chinese is by far the best known logographic writing system. For practical, everyday use, China has iirc about 5,500 characters. Our writing system has, iirc roughly 60.

      1. > This teaching apparently discourages attention to detail, which explains this consistent mistake. […] Silice and Slice ook similar,

        – Oook, ook. – The Librarian.

  2. yawn…..

    Yet another layer over a layer over a circuit description language…
    If people *learned VHDL properly*, that would reduce the need for all those hacks.
    And with the maturity of GHDL today, there is no excuse.

    1. Hm… It is the other way around – a language to describe platform-specific quirks such as DSP slices directly instead of relying on synthesis. Looks like it can be classified as a lower level than your typical Verilog (unless it is a pure netlist).

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