There is many a comment on these here pages along the lines of “Why did you use a microcontroller, when you could just have easily used a 555 timer!” And, yes, we sometimes agree with the sentiment, but when a chance comment seen by Hackaday.io user [Tim Böscke] suggested turning it around and building a microcontroller out of 555 timers, the gauntlet was well and truly thrown down. Now let’s be clear, this is not the first time we’ve come across this idea, there was a breadboard 555 based build ten years ago, but this is the first time we’ve seen it done by leveraging open source synthesis targeting a PCB!
The first logic element was a simple inverter, constructed by tying the TRIGger and THReShold pins together.
From there it was a simple matter of adding a few diode-resistor networks to the input, to effect a NAND2 gate and a NOR2 gate. Development was speeded up a bit by modeling the logic circuits in LTSpice, to find the best combination of part values. From these simple elements, all further logic functions could be implemented. Next a memory element was needed. As luck would have it, the 555 has a RS flip flop as part of its circuit, fed by dual comparator inputs. All that was needed was to bias the THRS input at Vdd/2 and then feed the data in via a pass transistor, and hey presto! a serviceable, albeit slow latch.
[Tim] has previously created a minimalist CPU called MCPU, with a mere four instructions, designed to fit in a 32 macrocell FPGA, so was able to reuse that design for this project. The fun part was to leverage the PCBFlow toolchain [Tim] maintains, which implements a Yosys synthesis flow with a custom place and route (PnR) backend. A liberty file was produced describing the circuits (macrocells) [Tim] wanted to make use of, then a synthesis script implemented the flow using Yosys/GHDL to elabourate the design, map it into the technology defined earlier, and write out a netlist the PnR tool could use. Helpfully Yosys also writes out a PDF of the design as well as a spice netlist. What a tool!
The PnR tool [Tim] created for PCBFlow was written in python, and outputs the XML format that Eagle can use. Its job is to place the macrocells (deliberately made square) by looking up the appropriate physical circuit, including all passives, dropping them into the PCB, adding the interconnects, and then optimising the layout using simulated annealing, optimising for minimal trace length. We think the result is pretty slick looking, and the approach is something that can easily be reused for other projects in the future.
Thanks [YGDES] for sending this in!