On my way to this year’s Hackaday SuperConference I saw an article on EE Times about someone taking the $22 Lattice iCEstick and turning it into a logic analyzer complete with a Python app to display the waveforms. This jumped out as pretty cool to me given that there really isn’t a ton of RAM on the stick, basically none that isn’t contained in the FPGA itself.
[Jenny List] has also written about the this application as created by [Kevin Hubbard] of Black Mesa Labs and [Al Williams] has a great set of posts about using this same $22 evaluation board doing ground up Verilog design using open source tools. Even if you don’t end up using the stick as a logic analyzer over the long haul, it’ll be very easy to find many other projects where you can recompile to invent a new purpose for it.
About the Stick
The Lattice iCEstick is a small FPGA evaluation PCB with only a little bit of support circuitry; basically just the FPGA, a clock, some SPI flash memory and a USB interface. There are also some connectors and pin pads as well as an IR transceiver to get signals on and off the assembly.
The FPGA itself is an iCE40HX1K with 160 logic blocks in it and up to 8 kilobytes of RAM, to me this sounds like a medium-small device, however since FPGA architectures differ I really can’t say for sure unless I wetre to load a couple of older designs I have used in the past for comparison.
I had been looking at the original SUMP.org analyzer for dropping onto one of my little custom FPGA boards I make when I am bored. I think of the logic analyzer application as a RAM pump (circular buffer controller) with a UART on one side and lots of I/O lines on the other. In general the amount of time desired to be captured at any particular clock frequency, translates directly to the amount of RAM needed. Protecting the FPGA from the harsh realities and in some cases the operating voltages present in the target system, is also important if using it for serious work.
[Kevin] refers to his design as SUMP2 and for good reason as there is some departure from the original SUMP architecture. The SUMP2 utilizes a simple lossless compression scheme called Run Length Encoding (RLE) where instead of sending a large number of 0’s or 1’s in a row, it sends a bit value and how many times to repeat that value before the next transition to a different bit state. The SUMP2 design compresses the data not just for sending it to the controlling computer but also before storing it in the limited amount of RAM in the iCE40. Again this means that it isn’t necessarily the amount of time (or number of sample clocks) that determines how much data is stored but instead the number of transitions recorded.
Looking at the block diagram it can be seen that the architecture also supports non-RLE encoded data sampling as denoted by the signals named “dwords” at the bottom left.
To get more of a hands-on experience I recommend downloading the entire project and then download the free FPGA design software iCEcube2 from Lattice, though they do require that the user submit the MAC address of their computer to obtain the license key to run the software.
In the video I step through loading the project and all for the steps up to compiling the RTL code and programming the FPGA. That’s my way of saying I am not going to repeat all of the steps here.
The other piece is the Python GUI which consists of two modules, a server module named bd_server.py which camps on a TCP port and interfaces to the USB, and the core sump.py module which runs as a pygame application. Before running the app a couple of modules need to be loaded (this is all contained in the installation instructions), namely pyserial, and pygame. I used the following commands (I am not a Python person, you may have a more insightful or efficient l way):
“python -m pip install -U pip setuptools” “python -m pip install -U pip pyserial” “python -m pip install -U pip wheel” “python -m pip install -U pip Pygame”
But wait, nothing is quite that simple, the instructions (and the video) walk the user through also setting VCP on the USB B port of the Lattice device driver. When and if you are successful you will be rewarded with the value for the virtual COM port.
The next thing to do is to run the bd_server app from the Windows CMD prompt “start bd_server.py”. It may fail the first time but it leaves behind a configuration file “bd_server.ini” in which the settings for the COM port and can be edited. Changing “AUTO” to the proper COM port appears to be a common requirement. Running the app a second time resulted in a “5 by 5” message indicating that it was properly running.
From here one is free to start analyzing and modifying if y’all have an interest to do so. For me, I found a line in sump.py and un-commented it so that the menu offered a direct way to make things bigger so my old eyes could actually see what I was looking at (turns out “home” and “end” always work for expanding the line height but I only know that from reading the code.
One note is that the FPGA used here is only 3.3V tolerant, [Kevin] has a public domain PCB up at OSHPark for converting to 5V.
If you have a serious need for a logic analyzer, use a serious analyzer, however if you want to spend a minimal amount of money and/or like open source stuff, check this out.