Programming FPGAs With Python

If you’ve ever wanted to jump into the world of FPGAs but don’t want to learn yet another language, you can now program an FPGA with Python. PyCPU converts very, very simple Python code into either VHDL or Verilog. From this, a hardware description can be uploaded to an FPGA.

The portion of the Python language supported by PyCPU is extremely minimal, with only ints being the only built-in data type supported. Of course ifs and whiles are still included along with all the assignments and operators. A new addition is a way to get digital IO access with Python, and obvious requirement if you’re going to be programming Silicon.

PyCPU surely won’t replace VHDL or Verilog anytime soon, but if you’re looking to get into FPGAs and the ‘telling a chip what to be’ paradigm it offers, it’s certainly a tool worth looking into.

Hats off to [hardsoftlucid] for sending this in. Our wonderful (we mean that, really) noticed a few mistakes when this was first posted. Those mistakes have been corrected.

22 thoughts on “Programming FPGAs With Python

  1. This seems pretty cool, but I recently got the hang of Verilog and found it easier to learn than Python. There’s so little to it, at least the synthesizable portions of the language.

    This appears to compile your code, and includes an embedded CPU to run it. The hardware equivalent of runtime I guess? That seems pretty useful. Can anyone answer if that’s how those C to HDL converters work?

    1. Some do, some don’t.

      I have only used CatapultC, Handel-C and Impulse C and all of those tools convert code direct to gates and flip-flops. Catapult analyzes code for loops and automatically unrolls them into pipelines.

      Handel-C on the other hand blindly converts variables to registers and program flow into a state machine without attempting to reuse any logic. If you want pipelines, you have to parallelize the code explicitly.

      Both Impulse C and Handel-C extend C with CSP style constructs to allow you to synchronise data between threads.

  2. This is a cool project and I think it’s great that more people are trying to make tools for others to get started with developing for FPGA’s, but I think that learning a new programming language (and a fairly simple one at that) is a good way to make sure you know that traditional programming is not effective and is not the point of FPGA’s.

    1. Depends on how you define usefull. If your purpose is to broaden and facilitate the use of FPGAs in the hacking community, than any addition to the already availlables programing languages is usefull.

      On the other hand, if you need barebone metal programing and efficiency, anything else than assembly isn’t usefull.

      As a simple guy without hacking skills but with python knowledge, this news is very interesting!

      1. A FPGA is a programmable logic chip, you typically don’t program it in assembly unless you have implemented a soft core processor. You use VHDL or Verilog to describe the logic which whatever program you’re running synthesizes and sends to the chip to be burnt in.

        Or am I missing something?

      2. You’re not missing anything. FPGAs are for developing highly customized hardware, glue logic, or even ASIC prototyping.
        Having a ‘python coprocessor’ is nice, and shows that if it is digital, it can be done in FPGAs.
        I can see use in place of state machines, but would’t it consume more resources?

  3. It is probably worth clarifying the difference between the two projects you’ve linked to (PyCpu, and MyHDL).

    MyHDL is a hardware description language comparable to VHDL or Verilog which uses a python like syntax (note: hardware description languages are very different to conventional programming languages, they are used for describing the physical arrangement of logic gates on silicon, programming languages are a series of instructions fed into a CPU which already exists on silicon).

    As far as I can tell PyCpu on the other hand is a very different project that just happens to be written in MyHDL. It is a CPU architecture which is optimized to run python byte-code. It seems like a really awesome idea given that most CPU architectures nowadays are targeted towards running compiled C. Really interested in what comes of the project.

    1. yep, you are right there is a little confusion beeing made in the article between the two projects.

      Especially in the sentence:
      The portion of the Python language supported by MyHDL is extremely minimal, with only ints being the only built-in data type supported.

      Myhdl really supports more datatypes. but pyCpu is limited to plane ints!!!

    2. A couple of corrections: MyHDL is implemented as a Python package, and therefore it is pure Python, not just python-like. HDLs support concepts like structure, time, hardware-friendly datatypes and fine-grained concurrency, but really are not that different from general programming languages. MyHDL shows this by implementing all these concepts within Python. Finally, HDLs are used to describe the functional behavior of hardware systems, not the physical arrangement of gates.

  4. I think you may have confused two separate projects. MyHDL is a hardware description language similar to Verilog and VHDL. It’s used for describing the layout of logic gates on a bit of silicon.

    PyCPU is a CPU design optimized for running a subset of python byte-code (which just happens to be written in MyHDL). This in itself is a really interesting idea as most CPU architectures are optimized for running compiled C code. Really interested in where this project ends up.

  5. While MyHDL of course doesn’t allow any extensive use of the Python language in the generated logic, it makes a great simulation testbench to verify the behavior of your design. For large sets of test data, VHDL will having you tearing your hair out. That said, there are a lot of constructs that can’t be built directly in MyHDL… If you’re working in tight timing constraints, this may be a problem when you go to synthesis.

  6. Sorry, but anyone who uses this to learn about FPGAs will be denying themselves a lot of enlightenment. Using an HDL is going to expose you to how FPGAs differ from CPUs and help you make that shift in your understanding. I get a kick out of that “aha!” moment as I’m sure most other HaD readers do. Anyway, I didn’t think it was too hard to learn enough Verilog to make some cool stuff.

    I think the project is neat, but I shudder to think of someone going this route because they don’t want to learn a new language.

  7. Please try it before making any judgements. This is not a new project, several years old and was built for real projects at a company that does FPGA work. This is not a toy or untested, it has been used in production. Supports a subset of python using RTL with a few datatype extensions to better support bits. You create and test your design in python interactively, convert to verilog and test using Verilog/GTK Wave. This project is far less limited than you might think and is a great way to get into FPGA’s.

  8. Note the following is incorrect!

    “MyHDL is extremely minimal”

    It should be

    “PyCPU is extremely minimal”.

    MyHDL is not minimal. For modeling all types are supported in MyHDL. Conversion has a subset of convertible types.

Leave a Reply to jandecaluweCancel reply

Please be kind and respectful to help make the comments section excellent. (Comment Policy)

This site uses Akismet to reduce spam. Learn how your comment data is processed.