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Hi Ben, thank you for your answer. The base frequency that is the input of my PLL is 30MHz, the output clock frequency is 90MHz. Rgds André > > What was your base frequency again, and what is the output frequency? > > Best regards, > > > > Ben

Check the mapping 'vmap' command which makes the association between actual simprim library and directory/path where it is stored. There issomething wrong there, typical error if you received a Modelsim Macro (.do file) exemple : vmap simprim C:/Xilinx/vhdl/mti_se/simprim or vmap simprim C:/Modeltech_xe_starter_5.7/xilinx/vhdl/simprim note the '/' instead of '\' in pathnames becauseModelsim is build upon tCL "Yaseen Zaidi" <yaseenzaidi@NETZERO.com> a écrit dans le message de news:a31921fc.0410130226.f1d4c03@posting.google.com... > I generate a testbench and then do Simulate Post-Translate VHDL Model > in ISE 6.2.03i. Modelsim frowns as follow: > > # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". > # No such file or directory. (errno = ENOENT) > # ** Error: rcvr_translate.vhd(18): Library simprim not found. > # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting > # ** Error: C:/Modeltech_5.8d/win32/vcom failed. > > I have compiled both simprim and unisim libraries in $Xilinx > directory. The testbench includes the following headers: > > library SIMPRIM; > use SIMPRIM.VCOMPONENTS.ALL; > use SIMPRIM.VPACKAGE.ALL; > > I like to do post translate/map/PAR timing simulation if I could only > get pass this error. > > Thanks, > > YZ

"Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote in message news:a31921fc.0410130226.f1d4c03@posting.google.com... > I generate a testbench and then do Simulate Post-Translate VHDL Model > in ISE 6.2.03i. Modelsim frowns as follow: > > # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". > # No such file or directory. (errno = ENOENT) > # ** Error: rcvr_translate.vhd(18): Library simprim not found. > # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting > # ** Error: C:/Modeltech_5.8d/win32/vcom failed. > > I have compiled both simprim and unisim libraries in $Xilinx > directory. The testbench includes the following headers: > > library SIMPRIM; > use SIMPRIM.VCOMPONENTS.ALL; > use SIMPRIM.VPACKAGE.ALL; > > I like to do post translate/map/PAR timing simulation if I could only > get pass this error. > > Thanks, > > YZ Looking at the notes of an old training course, it says compile the following source file in the following order: simprim_Vpackage.vhd simprim_Vcomponents.vhd simprim_VITAL.vhd Perhaps changing the order and adding VITAL may help. Regards, Jock

On Wed, 13 Oct 2004 07:58:55 +0200, Jan Bruns wrote: > Hallo. > > Where to find HDL-models of CLBs, so one could instantiate > them directly (or just to get a basic idea of what's efficiently > implementable)? The Xilinx datasheets aren't really clear about > the CLB-structure, I think. For example, after having read then > SpartanII datasheet, I still even don't know, how many signals go > out of a CLB, and which functions can be programmed with a CLB. > > Gruss > > Jan Bruns There are LUT models but not CLB models.

> > Just one more question. I remember that in the 10K series (yes, I'm an old guy!) the block RAM > (EAB?) could also work in a fully asyncronous mode while the Xilinx devices at that time did not > have this feature (and I used it a lot!). Is it the same for Cyclone and Spartan? Does Cyclone > supports fully async block RAM while Spartan does not? > No, this mode is not available in the Cyclone. It was available till the ACEXs. That change costed me some time to convert a project and I still would like to use asynch. block RAMs as larger LUTs. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/

"General Schvantzkoph": > Jan Bruns wrote: > > Where to find HDL-models of CLBs, so one could instantiate > > them directly (or just to get a basic idea of what's efficiently > > implementable)? The Xilinx datasheets aren't really clear about > > the CLB-structure, I think. For example, after having read then > > SpartanII datasheet, I still even don't know, how many signals go > > out of a CLB, and which functions can be programmed with a CLB. > There are LUT models but not CLB models. Hm, why? I've tried to create an LC-model, but I'm not sure, if it will synthesize correctly, if used within an slice/CLB-model: Gruss Jan Bruns `include "c:\xilinx\verilog\src\ise\unisim_comp.v" module spartanII_LC(gin1,gin2,gin3,gin4,carryin,directin,xorinL,xorinC, lutoutL,lutoutG,sumoutL,sumoutG,andoutL,carryoutL,carryoutG); input gin1,gin2,gin3,gin4; output lutoutL , lutoutG; output andoutL ; input carryin; output carryoutL,carryoutG; input directin; //may be andoutL (or "B"=directin ???) input xorinL , xorinC; output sumoutL, sumoutG; LUT4_D lut(.I0(gin1),.I1(gin2),.I2(gin3),.I3(gin4),.O(lutoutG),.LO(lutoutL)); // synthesis attribute INIT of lut is "abc7" MULT_AND multand(.I0(gin1),.I1(gin2),.LO(andoutL)); MUXCY_D carrylogic(.S(lutout),.DI(directin),.CI(carryin), .O(carryoutG),.LO(carryoutL)); XORCY_D xorcarry(.LI(xorinL),.CI(xorinC),.O(sumoutG),.LO(sumout)); endmodule

Jon, Yes, it is then called a BUFGCE (BUFG with enable). Austin Jon Beniston wrote: > Peter Alfke <peter@xilinx.com> wrote in message news:<BD90370B.95F8%peter@xilinx.com>... > >>Jonathan, the issue could be the asynchronous (?) selection of the clocks. I >>would assume that you can easily generate glitches, and no circuitry likes >>uncontrolled glitches on the global clock lines. >>Virtex global buffers include a mux that can be used to select between two >>inputs with glich-free operation guaranteed. > > > Can these (BUFGMUX) be used to implement clock-gating? (i.e. if one > input is the clock and the other is tied to 0)? > > Cheers, > Jon

Colin, Our SSO rules assume you have dedicated planes for Vccint, Vcco. If you do not have both a power and a ground plane for each of these supplies, the SSO numbers must be reduced. This also goes for simultaneously switching CLBs, and not just IOs. We assume a power and ground plane (yes that would be four layers just for power) for low inductance on the Vccint/Vcco. You might want to investigate the Point of Load concept (POL or POLA) from TI (US) and Belkin (Japan). By placing power supplies directly at the load, the loop inductance is greatly reduced. I have a SDRAM+2VP20 PCI pcb that has four layers, and operates very well. Perhaps you pay more for a more capable power supply, but you pay less for the PCB. Remember that V=-LdI/dt. There is no way to reduce ground and Vcc bounce without reducing either the I (current switched by reducing the number of things switching), or reducing the L (indutance). The time (dt) is not something that can be changed (as in internal nodes switch time is fixed by process and design). No amount of bypass caps will fix a bad pcb. Austin colin wrote: > Hi guys > > I have just finished routing a simple board with a 208 pin qfp spartan > 3. I have just used top and bottom layers and it is time to add the > power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and > vccaux. I have not routed any signal under the spartan on either layer > so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with > an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the > bottom layer. > > Just wondering if anyone can see any holes in this idea. > > thanks > > colin

"Jan Bruns" <post@abnuto.de> wrote in message news:ckig5v$rhn$1@online.de... > Hallo. > > Where to find HDL-models of CLBs, so one could instantiate > them directly (or just to get a basic idea of what's efficiently > implementable)? The Xilinx datasheets aren't really clear about > the CLB-structure, I think. For example, after having read then > SpartanII datasheet, I still even don't know, how many signals go > out of a CLB, and which functions can be programmed with a CLB. > > Gruss > > Jan Bruns The Spartan-II data sheet was a disappointment as far as the CLB graphics went, but... The Virtex (not Virtex-II) CLB structure is exactly the same as the Spartan-II and that data sheet *does* have beautiful detail. I've had a full-page print of the CLB graphic on my cubical wall for a few years now. The only thing I needed to add was the 0 and 1 input orientation to the F5, F6, and CY muxes.

"Antti Lukats" <antti@case2000.com> wrote in message news:<ckeg0t$fn5$05$1@news.t-online.com>... > "Varnavi" <sh_a_12@yahoo.com> wrote in message > news:a17d05bc.0410110754.713898b0@posting.google.com... > > Hi > > > > I am a graduate student and would like to implement the SATA I Host > > Controller Link and Transport layers in an FPGA for my Project. I am > > just starting on the RTL coding but would like to plan ahead for the > > verification of my RTL design. Can anyone guide me towards how I could > > write a testbench to verify my design and how doable is it. Are there > > any freely available Simulation testbenches for SATA I in which I can > > plug in my RTL code for verification. Let me know if there is a more > > apprpriate forum to address this question. Thanks. > > > > Varnavi > > 1) there is virtually nothing free for SATA > > are you doing it only as theoretical testbench or do you plan to verify it > in real FPGA design? > > There are NO SATA PHY IC's that can be purchased without major headache. > > And at least V2Pro/V4 RocketIO is not directly fully compliant with SATA > physical layer, so in case of FPGA verification what do you plan to use? > > Antti Hi Antti I am implementing only the link and transport layers as a RTL coding/FPGA Design project. So I guess I am interested in only a theoretical testbench to verify this. When researching the project it seemed that it would be a really difficult task to implement the Physical layer or would require high end FPGAs, so decided against it. Any Ideas on how I could verify just the link and transport layers in Simulation - what kind of a testbench would i require. If possible I would also like to program the design on to a low cost fpga board - if I do this is there any way I can verify the functionality on the board without additional hardware (Couldnt find any stand alone physical layer chips). I have some Verilog / FPGA design experience but new to SATA and have no idea how I am going to verify my design. Thanks Varnavi

Hi, We are in the process of designing a board using Xilinx Rocket-IO buffers. When I try to simulate certain nets driven by V2-Pro using Mentor Graphics HyperLynx simulator (we are using the EldoLynx Spice Simulator), I am getting an error message and the simulation halts. I have copied the error message below. Please look at ERROR-702 at the bottom of the attached file. kindly go through the same and suggest the needful. Thanks & Regards, Ravi -------------------ERROR MESSAGE------------------------------------- 1*******11-Oct-04 ******* ELDO v6.3_2.1 (Production version) (v6.3_2.1) *******21:22:33****** 0* SPICE TEST file for net Lsw00 - D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp 0**** INPUT LISTING 0*********************************************************************** 2 3 4 *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** 5 * * 6 * Be sure to check all settings if you make use of this test circuit. * 7 * * 8 *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** 9 10 11 12 * Output from HyperLynx SPICE Writer 13 * Created by CG-CoreEl on Date: Monday Oct. 11,2004 Time: 21:22:33 14 * Created with HyperLynx version: 7.2 build: 330 15 * Design file: CO_X_B1P.tln 16 * Special Settings: Coupled Lead-Parasitics 17 18 .TEMP 20.000000 19 20 V1003 1003 0 3.3 21 V1004 1004 0 0 22 V1005 1005 0 5 23 V1006 1006 0 5 24 V1007 1007 0 5 25 V1008 1008 0 5 26 V1009 1009 0 5 27 V1010 1010 0 5 28 V1011 1011 0 5 29 V1012 1012 0 0 30 VINP 1013 0 PWL 0.0000NS 0.00V 0.0392NS 1.00V 0.3920NS 1.00V 0.4312NS 0.00V 0.8000NS 0.00V 0.8392NS 1.00V 1.1920NS 1.00V 1.2312NS 0.00V 1.6000NS 0.00V 1.6392NS 1.00V 1.9920NS 1.00V 2.0312NS 0.00V 2.4000NS 0.00V 2.4392NS 1.00V 2.7920NS 1.00V 2.8312NS 0.00V 3.2000NS 0.00V 3.2392NS 1.00V 3.5920NS 1.00V 3.6312NS 0.00V 4.0000NS 0.00V 4.0392NS 1.00V 4.3920NS 1.00V 4.4312NS 0.00V 31 + 4.8000NS 0.00V 4.8392NS 1.00V 5.1920NS 1.00V 5.2312NS 0.00V 5.6000NS 0.00V 5.6392NS 1.00V 5.9920NS 1.00V 6.0312NS 0.00V 6.4000NS 0.00V 6.4392NS 1.00V 6.7920NS 1.00V 6.8312NS 0.00V 7.2000NS 0.00V 7.2392NS 1.00V 7.5920NS 1.00V 7.6312NS 0.00V 8.0000NS 0.00V 8.0392NS 1.00V 8.3920NS 1.00V 8.4312NS 0.00V 8.8000NS 0.00V 8.8392NS 1.00V 9.1920NS 1.00V 9.2312NS 0.00V 9.6000NS 0.00V 32 + 9.6392NS 1.00V 9.9920NS 1.00V 10.0312NS 0.00V 10.4000NS 0.00V 10.4392NS 1.00V 10.7920NS 1.00V 10.8312NS 0.00V 11.2000NS 0.00V 11.2392NS 1.00V 11.5920NS 1.00V 11.6312NS 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73.2312NS 0.00V 73.6000NS 0.00V 73.6392NS 1.00V 73.9920NS 1.00V 74.0312NS 0.00V 74.4000NS 0.00V 74.4392NS 1.00V 45 + 74.7920NS 1.00V 74.8312NS 0.00V 75.2000NS 0.00V 75.2392NS 1.00V 75.5920NS 1.00V 75.6312NS 0.00V 76.0000NS 0.00V 76.0392NS 1.00V 76.3920NS 1.00V 76.4312NS 0.00V 76.8000NS 0.00V 76.8392NS 1.00V 77.1920NS 1.00V 77.2312NS 0.00V 77.6000NS 0.00V 77.6392NS 1.00V 77.9920NS 1.00V 78.0312NS 0.00V 78.4000NS 0.00V 78.4392NS 1.00V 78.7920NS 1.00V 78.8312NS 0.00V 79.2000NS 0.00V 79.2392NS 1.00V 79.5920NS 1.00V 46 + 79.6312NS 0.00V 80.0000NS 0.00V 80.0392NS 1.00V 80.3920NS 1.00V 80.4312NS 0.00V 80.8000NS 0.00V 80.8392NS 1.00V 81.1920NS 1.00V 81.2312NS 0.00V 81.6000NS 0.00V 81.6392NS 1.00V 81.9920NS 1.00V 82.0312NS 0.00V 82.4000NS 0.00V 82.4392NS 1.00V 82.7920NS 1.00V 82.8312NS 0.00V 83.2000NS 0.00V 83.2392NS 1.00V 83.5920NS 1.00V 83.6312NS 0.00V 84.0000NS 0.00V 84.0392NS 1.00V 84.3920NS 1.00V 84.4312NS 0.00V 47 + 84.8000NS 0.00V 84.8392NS 1.00V 85.1920NS 1.00V 85.2312NS 0.00V 85.6000NS 0.00V 85.6392NS 1.00V 85.9920NS 1.00V 86.0312NS 0.00V 86.4000NS 0.00V 86.4392NS 1.00V 86.7920NS 1.00V 86.8312NS 0.00V 87.2000NS 0.00V 87.2392NS 1.00V 87.5920NS 1.00V 87.6312NS 0.00V 88.0000NS 0.00V 88.0392NS 1.00V 88.3920NS 1.00V 88.4312NS 0.00V 88.8000NS 0.00V 88.8392NS 1.00V 89.1920NS 1.00V 89.2312NS 0.00V 89.6000NS 0.00V 48 + 89.6392NS 1.00V 89.9920NS 1.00V 90.0312NS 0.00V 90.4000NS 0.00V 90.4392NS 1.00V 90.7920NS 1.00V 90.8312NS 0.00V 91.2000NS 0.00V 91.2392NS 1.00V 91.5920NS 1.00V 91.6312NS 0.00V 92.0000NS 0.00V 92.0392NS 1.00V 92.3920NS 1.00V 92.4312NS 0.00V 92.8000NS 0.00V 92.8392NS 1.00V 93.1920NS 1.00V 93.2312NS 0.00V 93.6000NS 0.00V 93.6392NS 1.00V 93.9920NS 1.00V 94.0312NS 0.00V 94.4000NS 0.00V 94.4392NS 1.00V 49 + 94.7920NS 1.00V 94.8312NS 0.00V 95.2000NS 0.00V 95.2392NS 1.00V 95.5920NS 1.00V 95.6312NS 0.00V 96.0000NS 0.00V 96.0392NS 1.00V 96.3920NS 1.00V 96.4312NS 0.00V 96.8000NS 0.00V 96.8392NS 1.00V 97.1920NS 1.00V 97.2312NS 0.00V 97.6000NS 0.00V 97.6392NS 1.00V 97.9920NS 1.00V 98.0312NS 0.00V 98.4000NS 0.00V 98.4392NS 1.00V 98.7920NS 1.00V 98.8312NS 0.00V 99.2000NS 0.00V 99.2392NS 1.00V 99.5920NS 1.00V 50 + 99.6312NS 0.00V 51 VINN 1014 0 PWL 0.0000NS 1.00V 0.0392NS 0.00V 0.3920NS 0.00V 0.4312NS 1.00V 0.8000NS 1.00V 0.8392NS 0.00V 1.1920NS 0.00V 1.2312NS 1.00V 1.6000NS 1.00V 1.6392NS 0.00V 1.9920NS 0.00V 2.0312NS 1.00V 2.4000NS 1.00V 2.4392NS 0.00V 2.7920NS 0.00V 2.8312NS 1.00V 3.2000NS 1.00V 3.2392NS 0.00V 3.5920NS 0.00V 3.6312NS 1.00V 4.0000NS 1.00V 4.0392NS 0.00V 4.3920NS 0.00V 4.4312NS 1.00V 52 + 4.8000NS 1.00V 4.8392NS 0.00V 5.1920NS 0.00V 5.2312NS 1.00V 5.6000NS 1.00V 5.6392NS 0.00V 5.9920NS 0.00V 6.0312NS 1.00V 6.4000NS 1.00V 6.4392NS 0.00V 6.7920NS 0.00V 6.8312NS 1.00V 7.2000NS 1.00V 7.2392NS 0.00V 7.5920NS 0.00V 7.6312NS 1.00V 8.0000NS 1.00V 8.0392NS 0.00V 8.3920NS 0.00V 8.4312NS 1.00V 8.8000NS 1.00V 8.8392NS 0.00V 9.1920NS 0.00V 9.2312NS 1.00V 9.6000NS 1.00V 53 + 9.6392NS 0.00V 9.9920NS 0.00V 10.0312NS 1.00V 10.4000NS 1.00V 10.4392NS 0.00V 10.7920NS 0.00V 10.8312NS 1.00V 11.2000NS 1.00V 11.2392NS 0.00V 11.5920NS 0.00V 11.6312NS 1.00V 12.0000NS 1.00V 12.0392NS 0.00V 12.3920NS 0.00V 12.4312NS 1.00V 12.8000NS 1.00V 12.8392NS 0.00V 13.1920NS 0.00V 13.2312NS 1.00V 13.6000NS 1.00V 13.6392NS 0.00V 13.9920NS 0.00V 14.0312NS 1.00V 14.4000NS 1.00V 14.4392NS 0.00V 54 + 14.7920NS 0.00V 14.8312NS 1.00V 15.2000NS 1.00V 15.2392NS 0.00V 15.5920NS 0.00V 15.6312NS 1.00V 16.0000NS 1.00V 16.0392NS 0.00V 16.3920NS 0.00V 16.4312NS 1.00V 16.8000NS 1.00V 16.8392NS 0.00V 17.1920NS 0.00V 17.2312NS 1.00V 17.6000NS 1.00V 17.6392NS 0.00V 17.9920NS 0.00V 18.0312NS 1.00V 18.4000NS 1.00V 18.4392NS 0.00V 18.7920NS 0.00V 18.8312NS 1.00V 19.2000NS 1.00V 19.2392NS 0.00V 19.5920NS 0.00V 55 + 19.6312NS 1.00V 20.0000NS 1.00V 20.0392NS 0.00V 20.3920NS 0.00V 20.4312NS 1.00V 20.8000NS 1.00V 20.8392NS 0.00V 21.1920NS 0.00V 21.2312NS 1.00V 21.6000NS 1.00V 21.6392NS 0.00V 21.9920NS 0.00V 22.0312NS 1.00V 22.4000NS 1.00V 22.4392NS 0.00V 22.7920NS 0.00V 22.8312NS 1.00V 23.2000NS 1.00V 23.2392NS 0.00V 23.5920NS 0.00V 23.6312NS 1.00V 24.0000NS 1.00V 24.0392NS 0.00V 24.3920NS 0.00V 24.4312NS 1.00V 56 + 24.8000NS 1.00V 24.8392NS 0.00V 25.1920NS 0.00V 25.2312NS 1.00V 25.6000NS 1.00V 25.6392NS 0.00V 25.9920NS 0.00V 26.0312NS 1.00V 26.4000NS 1.00V 26.4392NS 0.00V 26.7920NS 0.00V 26.8312NS 1.00V 27.2000NS 1.00V 27.2392NS 0.00V 27.5920NS 0.00V 27.6312NS 1.00V 28.0000NS 1.00V 28.0392NS 0.00V 28.3920NS 0.00V 28.4312NS 1.00V 28.8000NS 1.00V 28.8392NS 0.00V 29.1920NS 0.00V 29.2312NS 1.00V 29.6000NS 1.00V 57 + 29.6392NS 0.00V 29.9920NS 0.00V 30.0312NS 1.00V 30.4000NS 1.00V 30.4392NS 0.00V 30.7920NS 0.00V 30.8312NS 1.00V 31.2000NS 1.00V 31.2392NS 0.00V 31.5920NS 0.00V 31.6312NS 1.00V 32.0000NS 1.00V 32.0392NS 0.00V 32.3920NS 0.00V 32.4312NS 1.00V 32.8000NS 1.00V 32.8392NS 0.00V 33.1920NS 0.00V 33.2312NS 1.00V 33.6000NS 1.00V 33.6392NS 0.00V 33.9920NS 0.00V 34.0312NS 1.00V 34.4000NS 1.00V 34.4392NS 0.00V 58 + 34.7920NS 0.00V 34.8312NS 1.00V 35.2000NS 1.00V 35.2392NS 0.00V 35.5920NS 0.00V 35.6312NS 1.00V 36.0000NS 1.00V 36.0392NS 0.00V 36.3920NS 0.00V 36.4312NS 1.00V 36.8000NS 1.00V 36.8392NS 0.00V 37.1920NS 0.00V 37.2312NS 1.00V 37.6000NS 1.00V 37.6392NS 0.00V 37.9920NS 0.00V 38.0312NS 1.00V 38.4000NS 1.00V 38.4392NS 0.00V 38.7920NS 0.00V 38.8312NS 1.00V 39.2000NS 1.00V 39.2392NS 0.00V 39.5920NS 0.00V 59 + 39.6312NS 1.00V 40.0000NS 1.00V 40.0392NS 0.00V 40.3920NS 0.00V 40.4312NS 1.00V 40.8000NS 1.00V 40.8392NS 0.00V 41.1920NS 0.00V 41.2312NS 1.00V 41.6000NS 1.00V 41.6392NS 0.00V 41.9920NS 0.00V 42.0312NS 1.00V 42.4000NS 1.00V 42.4392NS 0.00V 42.7920NS 0.00V 42.8312NS 1.00V 43.2000NS 1.00V 43.2392NS 0.00V 43.5920NS 0.00V 43.6312NS 1.00V 44.0000NS 1.00V 44.0392NS 0.00V 44.3920NS 0.00V 44.4312NS 1.00V 60 + 44.8000NS 1.00V 44.8392NS 0.00V 45.1920NS 0.00V 45.2312NS 1.00V 45.6000NS 1.00V 45.6392NS 0.00V 45.9920NS 0.00V 46.0312NS 1.00V 46.4000NS 1.00V 46.4392NS 0.00V 46.7920NS 0.00V 46.8312NS 1.00V 47.2000NS 1.00V 47.2392NS 0.00V 47.5920NS 0.00V 47.6312NS 1.00V 48.0000NS 1.00V 48.0392NS 0.00V 48.3920NS 0.00V 48.4312NS 1.00V 48.8000NS 1.00V 48.8392NS 0.00V 49.1920NS 0.00V 49.2312NS 1.00V 49.6000NS 1.00V 61 + 49.6392NS 0.00V 49.9920NS 0.00V 50.0312NS 1.00V 50.4000NS 1.00V 50.4392NS 0.00V 50.7920NS 0.00V 50.8312NS 1.00V 51.2000NS 1.00V 51.2392NS 0.00V 51.5920NS 0.00V 51.6312NS 1.00V 52.0000NS 1.00V 52.0392NS 0.00V 52.3920NS 0.00V 52.4312NS 1.00V 52.8000NS 1.00V 52.8392NS 0.00V 53.1920NS 0.00V 53.2312NS 1.00V 53.6000NS 1.00V 53.6392NS 0.00V 53.9920NS 0.00V 54.0312NS 1.00V 54.4000NS 1.00V 54.4392NS 0.00V 62 + 54.7920NS 0.00V 54.8312NS 1.00V 55.2000NS 1.00V 55.2392NS 0.00V 55.5920NS 0.00V 55.6312NS 1.00V 56.0000NS 1.00V 56.0392NS 0.00V 56.3920NS 0.00V 56.4312NS 1.00V 56.8000NS 1.00V 56.8392NS 0.00V 57.1920NS 0.00V 57.2312NS 1.00V 57.6000NS 1.00V 57.6392NS 0.00V 57.9920NS 0.00V 58.0312NS 1.00V 58.4000NS 1.00V 58.4392NS 0.00V 58.7920NS 0.00V 58.8312NS 1.00V 59.2000NS 1.00V 59.2392NS 0.00V 59.5920NS 0.00V 63 + 59.6312NS 1.00V 60.0000NS 1.00V 60.0392NS 0.00V 60.3920NS 0.00V 60.4312NS 1.00V 60.8000NS 1.00V 60.8392NS 0.00V 61.1920NS 0.00V 61.2312NS 1.00V 61.6000NS 1.00V 61.6392NS 0.00V 61.9920NS 0.00V 62.0312NS 1.00V 62.4000NS 1.00V 62.4392NS 0.00V 62.7920NS 0.00V 62.8312NS 1.00V 63.2000NS 1.00V 63.2392NS 0.00V 63.5920NS 0.00V 63.6312NS 1.00V 64.0000NS 1.00V 64.0392NS 0.00V 64.3920NS 0.00V 64.4312NS 1.00V 64 + 64.8000NS 1.00V 64.8392NS 0.00V 65.1920NS 0.00V 65.2312NS 1.00V 65.6000NS 1.00V 65.6392NS 0.00V 65.9920NS 0.00V 66.0312NS 1.00V 66.4000NS 1.00V 66.4392NS 0.00V 66.7920NS 0.00V 66.8312NS 1.00V 67.2000NS 1.00V 67.2392NS 0.00V 67.5920NS 0.00V 67.6312NS 1.00V 68.0000NS 1.00V 68.0392NS 0.00V 68.3920NS 0.00V 68.4312NS 1.00V 68.8000NS 1.00V 68.8392NS 0.00V 69.1920NS 0.00V 69.2312NS 1.00V 69.6000NS 1.00V 65 + 69.6392NS 0.00V 69.9920NS 0.00V 70.0312NS 1.00V 70.4000NS 1.00V 70.4392NS 0.00V 70.7920NS 0.00V 70.8312NS 1.00V 71.2000NS 1.00V 71.2392NS 0.00V 71.5920NS 0.00V 71.6312NS 1.00V 72.0000NS 1.00V 72.0392NS 0.00V 72.3920NS 0.00V 72.4312NS 1.00V 72.8000NS 1.00V 72.8392NS 0.00V 73.1920NS 0.00V 73.2312NS 1.00V 73.6000NS 1.00V 73.6392NS 0.00V 73.9920NS 0.00V 74.0312NS 1.00V 74.4000NS 1.00V 74.4392NS 0.00V 66 + 74.7920NS 0.00V 74.8312NS 1.00V 75.2000NS 1.00V 75.2392NS 0.00V 75.5920NS 0.00V 75.6312NS 1.00V 76.0000NS 1.00V 76.0392NS 0.00V 76.3920NS 0.00V 76.4312NS 1.00V 76.8000NS 1.00V 76.8392NS 0.00V 77.1920NS 0.00V 77.2312NS 1.00V 77.6000NS 1.00V 77.6392NS 0.00V 77.9920NS 0.00V 78.0312NS 1.00V 78.4000NS 1.00V 78.4392NS 0.00V 78.7920NS 0.00V 78.8312NS 1.00V 79.2000NS 1.00V 79.2392NS 0.00V 79.5920NS 0.00V 67 + 79.6312NS 1.00V 80.0000NS 1.00V 80.0392NS 0.00V 80.3920NS 0.00V 80.4312NS 1.00V 80.8000NS 1.00V 80.8392NS 0.00V 81.1920NS 0.00V 81.2312NS 1.00V 81.6000NS 1.00V 81.6392NS 0.00V 81.9920NS 0.00V 82.0312NS 1.00V 82.4000NS 1.00V 82.4392NS 0.00V 82.7920NS 0.00V 82.8312NS 1.00V 83.2000NS 1.00V 83.2392NS 0.00V 83.5920NS 0.00V 83.6312NS 1.00V 84.0000NS 1.00V 84.0392NS 0.00V 84.3920NS 0.00V 84.4312NS 1.00V 68 + 84.8000NS 1.00V 84.8392NS 0.00V 85.1920NS 0.00V 85.2312NS 1.00V 85.6000NS 1.00V 85.6392NS 0.00V 85.9920NS 0.00V 86.0312NS 1.00V 86.4000NS 1.00V 86.4392NS 0.00V 86.7920NS 0.00V 86.8312NS 1.00V 87.2000NS 1.00V 87.2392NS 0.00V 87.5920NS 0.00V 87.6312NS 1.00V 88.0000NS 1.00V 88.0392NS 0.00V 88.3920NS 0.00V 88.4312NS 1.00V 88.8000NS 1.00V 88.8392NS 0.00V 89.1920NS 0.00V 89.2312NS 1.00V 89.6000NS 1.00V 69 + 89.6392NS 0.00V 89.9920NS 0.00V 90.0312NS 1.00V 90.4000NS 1.00V 90.4392NS 0.00V 90.7920NS 0.00V 90.8312NS 1.00V 91.2000NS 1.00V 91.2392NS 0.00V 91.5920NS 0.00V 91.6312NS 1.00V 92.0000NS 1.00V 92.0392NS 0.00V 92.3920NS 0.00V 92.4312NS 1.00V 92.8000NS 1.00V 92.8392NS 0.00V 93.1920NS 0.00V 93.2312NS 1.00V 93.6000NS 1.00V 93.6392NS 0.00V 93.9920NS 0.00V 94.0312NS 1.00V 94.4000NS 1.00V 94.4392NS 0.00V 70 + 94.7920NS 0.00V 94.8312NS 1.00V 95.2000NS 1.00V 95.2392NS 0.00V 95.5920NS 0.00V 95.6312NS 1.00V 96.0000NS 1.00V 96.0392NS 0.00V 96.3920NS 0.00V 96.4312NS 1.00V 96.8000NS 1.00V 96.8392NS 0.00V 97.1920NS 0.00V 97.2312NS 1.00V 97.6000NS 1.00V 97.6392NS 0.00V 97.9920NS 0.00V 98.0312NS 1.00V 98.4000NS 1.00V 98.4392NS 0.00V 98.7920NS 0.00V 98.8312NS 1.00V 99.2000NS 1.00V 99.2392NS 0.00V 99.5920NS 0.00V 71 + 99.6312NS 1.00V 72 V001 1002 0 0.0 73 X1 1013 1014 1 2 3 4 CO_X_B1P 74 75 76 77 * Node 1 = S12P1.B5 (driver) Library=rocketio_rx.inc model=rx_esd_term_N_couple 78 * Node 2 = S1P2.B7 Library=rocketio_rx.inc model=rx_esd_term_N_couple 79 * Node 3 = S12P1.A5 (driver) Library=rocketio_rx.inc model=rx_esd_term_N_couple 80 * Node 4 = S1P2.A7 Library=rocketio_rx.inc model=rx_esd_term_N_couple 81 82 * Node 0 = Gnd (Common Return) 83 84 *<<<Spice Models>>> 85 *.subckt rx_esd_term_N_couple CTD_VDD_15 CTD_VDD_25 CTD_VSS RXN_in RXN_out 86 X2 1003 1003 0 NC0 3 NC1 1 1003 NC2 RX_ESD_TERM_N_COUPLE 87 *.subckt rx_esd_term_N_couple CTD_VDD_15 CTD_VDD_25 CTD_VSS RXN_in RXN_out 88 X3 1003 1003 0 4 NC3 2 NC4 1003 NC5 RX_ESD_TERM_N_COUPLE 89 .OPTIONS SEARCH='D:\' 90 .OPTIONS SEARCH='D:\MENTOR GRAPHICS\2004\HYPERLYNX\LIBS\' 91 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO KIT\SIS_KIT_V2P_V3.6\EXAMPLE\HYP_BP\' 92 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO KIT\SIS_KIT_V2P_V3.6\IC_MODELS\ELDO\' 93 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO KIT\SIS_KIT_V2P_V3.6\CONNECTOR_MODELS\TERADYNE_HSD\MODELS\' 94 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO KIT\SIS_KIT_V2P_V3.6\CONNECTOR_MODELS\TYCO_HSSDC2\MODELS\' 95 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO KIT\SIS_KIT_V2P_V3.6\VIA_MODELS\' 96 .OPTIONS SEARCH='D:\PROJECTS\XALTED\SIMULATION\MODELS\' 97 .OPTIONS SEARCH='D:\PROJECTS\XALTED\SIMULATION\4X-BPC\' 98 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO_KIT\SIS_KIT_V2P_V3.6\EXAMPLE\HYP_BP\' 99 .OPTIONS SEARCH='D:\PROJECTS\NATSEM\SPICE_INFO\NETLIST\' 100 .OPTIONS SEARCH='D:\PROJECTS\IWAVE\MODELS\' 101 .OPTIONS SEARCH='D:\PROJECTS\CENTILLIUM\MOTHERBOARD\MODELS\' 102 ** including D:\rocketio_rx.inc 1 ************************************************ 2 ************ Xilinx RocketIO RX ************ 3 ***************** (start) **************** 4 ************************************************ 5 6 .SUBCKT RX_LOOPBACK_TERM CTD_VDD CTD_VSS LBN LBP EN 25 .ENDS RX_LOOPBACK_TERM 26 27 ** End of subcircuit definition. 28 29 .SUBCKT RX_AFE_LOAD2 CTD_VDD CTD_VSS R_2 R_1 R_0 SOURCE 48 .ENDS RX_AFE_LOAD2 49 50 ** End of subcircuit definition. 51 52 .SUBCKT RX_AFE_LOAD1 CTD_VDD CTD_VSS LB RA_1 RA_0 RB_1 RB_0 SOURCE 108 .ENDS RX_AFE_LOAD1 109 110 ** End of subcircuit definition. 111 112 .SUBCKT RX_AFE_R1 CTD_VDD CTD_VSS IN_100U_LB LB LBN LBP OUTN OUTP PD RDN 113 + RDP RX_FE_I_1 RX_FE_I_0 RX_FE_R_9 RX_FE_R_8 RX_FE_R_7 RX_FE_R_6 114 + RX_FE_R_5 RX_FE_R_4 RX_FE_R_3 RX_FE_R_2 RX_FE_R_1 RX_FE_R_0 170 .ENDS RX_AFE_R1 171 172 ** End of subcircuit definition. 173 174 .SUBCKT RX_AC_CAP P1 P2 9 .ENDS RX_AC_CAP 10 11 ** End of subcircuit definition. 12 13 .SUBCKT RX_1M_R CTD_VDD TERM1 TERM2 68 .ENDS RX_1M_R 69 70 ** End of subcircuit definition. 71 72 .SUBCKT RX_AC_R CTD_VDD IPULSE_1 IPULSE_2 VREF 10 .ENDS RX_AC_R 11 12 ** End of subcircuit definition. 13 14 .SUBCKT RX_ESD_TERM_N_COUPLE CTD_VDD_15 CTD_VDD_25 CTD_VSS RXN_IN RXN_OUT 15 + RXP_IN RXP_OUT VTRX VREF 56 .ENDS RX_ESD_TERM_N_COUPLE 57 58 ** End of subcircuit definition. 59 60 .SUBCKT RX CTD_VDD_15 CTD_VDD_25 DATA_N DATA_P LB_N LB_P RXN RXP 61 + RX_GND VTRX LOOPBACK_1 PD RX_FE_I_1 RX_FE_I_0 RX_FE_R_9 RX_FE_R_8 62 + RX_FE_R_7 RX_FE_R_6 RX_FE_R_5 RX_FE_R_4 RX_FE_R_3 RX_FE_R_2 63 + RX_FE_R_1 RX_FE_R_0 VREF_AFE 59 .ENDS RX 60 61 ** End of subcircuit definition. 62 63 64 ************************************************ 65 ************ Xilinx RocketIO RX ************ 66 ****************** (end) ***************** 67 ************************************************ 68 102 103 *<<<End Spice Models>>> 104 105 106 ** including D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp 1 * Netlist for net Lsw00 - D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp 2 3 4 * Output from HyperLynx SPICE Writer 5 * Created by CG-CoreEl on Date: Monday Oct. 11,2004 Time: 21:22:33 6 * Created with HyperLynx version: 7.2 build: 330 7 * Design file: CO_X_B1P.tln 8 * Special Settings: Coupled Lead-Parasitics 9 10 11 .SUBCKT CO_X_B1P VINP VINN 101 111 114 124 12 13 * Node # = <Reference Designator>.<pin name> 14 ********************************************** 15 * Node 101 = S12P1.B5 (driver) Library=rocketio_rx.inc model=rx_esd_term_N_couple 16 * Node 111 = S1P2.B7 Library=rocketio_rx.inc model=rx_esd_term_N_couple 17 * Node 114 = S12P1.A5 (driver) Library=rocketio_rx.inc model=rx_esd_term_N_couple 18 * Node 124 = S1P2.A7 Library=rocketio_rx.inc model=rx_esd_term_N_couple 19 20 * Node 0 = Gnd (Common Return) 21 22 23 T001 101 0 103 0 Z0=5.800000E+001 TD=2.000000E-010 24 W002 N=1 103 0 104 0 RLGCmodel=Model_W002 L=0.00369267 MULTIDEBYE=1 25 W008 N=1 109 0 111 0 RLGCmodel=Model_W008 L=0.0165475 MULTIDEBYE=1 26 T009 114 0 116 0 Z0=5.800000E+001 TD=2.000000E-010 27 W010 N=1 116 0 117 0 RLGCmodel=Model_W010 L=0.00147276 MULTIDEBYE=1 28 W016 N=1 122 0 124 0 RLGCmodel=Model_W016 L=0.019668 MULTIDEBYE=1 29 30 WCOND_000 121 108 0 122 109 0 RLGCmodel=Cond_000 N=2 L=0.008352 MULTIDEBYE=1 31 WCOND_001 120 107 0 121 108 0 RLGCmodel=Cond_001 N=2 L=0.023949 MULTIDEBYE=1 32 WCOND_002 119 106 0 120 107 0 RLGCmodel=Cond_002 N=2 L=0.210226 MULTIDEBYE=1 33 WCOND_003 105 118 0 106 119 0 RLGCmodel=Cond_003 N=2 L=0.011608 MULTIDEBYE=1 34 WCOND_004 117 104 0 118 105 0 RLGCmodel=Cond_004 N=2 L=0.013277 MULTIDEBYE=1 35 V1 1 0 0.00 36 **** Transmission line models *********************** 37 38 ********************************* 39 * Single uncoupled transmission line 40 41 .MODEL MODEL_W002 W MODELTYPE=RLGC N=1 42 * Lo (H/m) 43 + LO = 44 + 3.59892E-007 45 46 * Co (F/m) 47 + CO = 48 + 1.39123E-010 49 50 * Ro (Ohm/m) 51 + RO = 52 + 4.4911 53 54 * Go (S/m) 55 + GO = 56 + 0 57 58 * Rs (Ohm/m-sqrt(Hz)) 59 + RS = 60 + 0.000578602 61 62 * Gd (S/m-Hz) 63 + GD = 64 + 2.78246E-012 65 66 67 ********************************* 68 * Single uncoupled transmission line 69 70 .MODEL MODEL_W008 W MODELTYPE=RLGC N=1 71 * Lo (H/m) 72 + LO = 73 + 3.59892E-007 74 75 * Co (F/m) 76 + CO = 77 + 1.39123E-010 78 79 * Ro (Ohm/m) 80 + RO = 81 + 4.4911 82 83 * Go (S/m) 84 + GO = 85 + 0 86 87 * Rs (Ohm/m-sqrt(Hz)) 88 + RS = 89 + 0.000578602 90 91 * Gd (S/m-Hz) 92 + GD = 93 + 2.78246E-012 94 95 96 ********************************* 97 * Single uncoupled transmission line 98 99 .MODEL MODEL_W010 W MODELTYPE=RLGC N=1 100 * Lo (H/m) 101 + LO = 102 + 3.59892E-007 103 104 * Co (F/m) 105 + CO = 106 + 1.39123E-010 107 108 * Ro (Ohm/m) 109 + RO = 110 + 4.4911 111 112 * Go (S/m) 113 + GO = 114 + 0 115 116 * Rs (Ohm/m-sqrt(Hz)) 117 + RS = 118 + 0.000578602 119 120 * Gd (S/m-Hz) 121 + GD = 122 + 2.78246E-012 123 124 125 ********************************* 126 * Single uncoupled transmission line 127 128 .MODEL MODEL_W016 W MODELTYPE=RLGC N=1 129 * Lo (H/m) 130 + LO = 131 + 3.59892E-007 132 133 * Co (F/m) 134 + CO = 135 + 1.39123E-010 136 137 * Ro (Ohm/m) 138 + RO = 139 + 4.4911 140 141 * Go (S/m) 142 + GO = 143 + 0 144 145 * Rs (Ohm/m-sqrt(Hz)) 146 + RS = 147 + 0.000578602 148 149 * Gd (S/m-Hz) 150 + GD = 151 + 2.78246E-012 152 153 ********************************* 154 * RLGC model created by HyperLynx SPICE generator 155 * 156 .MODEL COND_000 W MODELTYPE=RLGC N=2 157 * Lo (H/m) 158 + LO = 159 + 3.5972E-007 160 + 2.63282E-008 3.5972E-007 161 162 * Co (F/m) 163 + CO = 164 + 1.39939E-010 165 + -1.02423E-011 1.39939E-010 166 167 * Ro (Ohm/m) 168 + RO = 169 + 4.4911 170 + 0 4.4911 171 172 * Go (S/m) 173 + GO = 174 + 0 175 + 0 0 176 177 * Rs (Ohm/m-sqrt(Hz)) 178 + RS = 179 + 0.00106555 180 + 2.10618E-005 0.00106555 181 182 * Gd (S/m-Hz) 183 + GD = 184 + 1.75853E-011 185 + -1.28708E-012 1.75853E-011 186 187 ********************************* 188 189 ********************************* 190 * RLGC model created by HyperLynx SPICE generator 191 * 192 .MODEL COND_001 W MODELTYPE=RLGC N=2 193 * Lo (H/m) 194 + LO = 195 + 3.5972E-007 196 + 2.63128E-008 3.5972E-007 197 198 * Co (F/m) 199 + CO = 200 + 1.39938E-010 201 + -1.02362E-011 1.39938E-010 202 203 * Ro (Ohm/m) 204 + RO = 205 + 4.4911 206 + 0 4.4911 207 208 * Go (S/m) 209 + GO = 210 + 0 211 + 0 0 212 213 * Rs (Ohm/m-sqrt(Hz)) 214 + RS = 215 + 0.00106552 216 + 2.10544E-005 0.00106552 217 218 * Gd (S/m-Hz) 219 + GD = 220 + 1.75852E-011 221 + -1.28632E-012 1.75852E-011 222 223 ********************************* 224 225 ********************************* 226 * RLGC model created by HyperLynx SPICE generator 227 * 228 .MODEL COND_002 W MODELTYPE=RLGC N=2 229 * Lo (H/m) 230 + LO = 231 + 3.5972E-007 232 + 2.63282E-008 3.5972E-007 233 234 * Co (F/m) 235 + CO = 236 + 1.39939E-010 237 + -1.02423E-011 1.39939E-010 238 239 * Ro (Ohm/m) 240 + RO = 241 + 4.4911 242 + 0 4.4911 243 244 * Go (S/m) 245 + GO = 246 + 0 247 + 0 0 248 249 * Rs (Ohm/m-sqrt(Hz)) 250 + RS = 251 + 0.00106555 252 + 2.10618E-005 0.00106555 253 254 * Gd (S/m-Hz) 255 + GD = 256 + 1.75853E-011 257 + -1.28708E-012 1.75853E-011 258 259 ********************************* 260 261 ********************************* 262 * RLGC model created by HyperLynx SPICE generator 263 * 264 .MODEL COND_003 W MODELTYPE=RLGC N=2 265 * Lo (H/m) 266 + LO = 267 + 3.5972E-007 268 + 2.63282E-008 3.5972E-007 269 270 * Co (F/m) 271 + CO = 272 + 1.39939E-010 273 + -1.02423E-011 1.39939E-010 274 275 * Ro (Ohm/m) 276 + RO = 277 + 4.4911 278 + 0 4.4911 279 280 * Go (S/m) 281 + GO = 282 + 0 283 + 0 0 284 285 * Rs (Ohm/m-sqrt(Hz)) 286 + RS = 287 + 0.00106555 288 + 2.10618E-005 0.00106555 289 290 * Gd (S/m-Hz) 291 + GD = 292 + 1.75853E-011 293 + -1.28708E-012 1.75853E-011 294 295 ********************************* 296 297 ********************************* 298 * RLGC model created by HyperLynx SPICE generator 299 * 300 .MODEL COND_004 W MODELTYPE=RLGC N=2 301 * Lo (H/m) 302 + LO = 303 + 3.5972E-007 304 + 2.63282E-008 3.5972E-007 305 306 * Co (F/m) 307 + CO = 308 + 1.39939E-010 309 + -1.02423E-011 1.39939E-010 310 311 * Ro (Ohm/m) 312 + RO = 313 + 4.4911 314 + 0 4.4911 315 316 * Go (S/m) 317 + GO = 318 + 0 319 + 0 0 320 321 * Rs (Ohm/m-sqrt(Hz)) 322 + RS = 323 + 0.00106555 324 + 2.10618E-005 0.00106555 325 326 * Gd (S/m-Hz) 327 + GD = 328 + 1.75853E-011 329 + -1.28708E-012 1.75853E-011 330 331 ********************************* 332 333 334 **** End Transmission line models ******************* 335 336 .ENDS 106 107 108 *<<<Scope Time>>> 109 .TRAN 5.2PS 100.02NS 110 .OPTION step=5.2e-012 111 112 113 *** Start inclusions 114 *** End inclusions 115 116 .PRINT TRAN V(3 ) 117 V126 3 126 0.0 118 .PRINT TRAN V(1 ) 119 V127 1 127 0.0 120 121 .END End of file ***** 0 error(s). ***** 0 warning(s). ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_VDDCDM": Undeclared subcircuit reference. Instance appeared near source line 14 ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_VSSCDM": Undeclared subcircuit reference. Instance appeared near source line 14 ERROR 702: SUBCKT "RX_1M_R.ANA_RPPO1RPOP": Undeclared subcircuit reference. Instance appeared near source line 12 ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_HBM": Undeclared subcircuit reference. Instance appeared near source line 14 ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.ANA_RPPO1RPOP": Undeclared subcircuit reference. Instance appeared near source line 14 ***** GENERATION ... ***** 5 error(s). ***** 0 warning(s). INFORMATION ABOUT COMPILATION Memory space allocated (bytes): 551274 0 elements 0 nodes 0 input signals Check your input netlist... Job started at 11-Oct-2004 21:22:33 Job end at 11-Oct-2004 21:22:34 Run on Win

Hi Does anyone know the cheapest way to generate the 1.2V needed for spartan3. All the linear regs that say they go down to 1.2 have a vref that is 1.2 to 1.3V. All I can think is that the leakage on the adj pin when it is grounded makes some difference or that 1.2 is the marketing b*ll. Colin

Ravi, Looks like a file is missing with some subcircuits in it. The error messages are complaining that certain elements are missing from the simulation. Check that all files are downloaded, present, and in the right place. Austin Ravi wrote: > Hi, > > We are in the process of designing a board using Xilinx Rocket-IO > buffers. When I try to simulate certain nets driven by V2-Pro using > Mentor Graphics HyperLynx simulator (we are using the EldoLynx Spice > Simulator), I am getting an error message and the simulation halts. I > have copied the error message below. Please look at ERROR-702 at the > bottom of the attached file. > kindly go through the same and suggest the needful. > > Thanks & Regards, > > Ravi > > -------------------ERROR MESSAGE------------------------------------- > > > > 1*******11-Oct-04 ******* ELDO v6.3_2.1 (Production version) > (v6.3_2.1) *******21:22:33****** > > 0* SPICE TEST file for net Lsw00 - > D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp > > > 0**** INPUT LISTING > > 0*********************************************************************** > 2 > > 3 > > 4 *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE > *** NOTE *** > 5 * > * > 6 * Be sure to check all settings if you make use of this test > circuit. * > 7 * > * > 8 *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE *** NOTE > *** NOTE *** > 9 > > 10 > > 11 > > 12 * Output from HyperLynx SPICE Writer > 13 * Created by CG-CoreEl on Date: Monday Oct. 11,2004 Time: > 21:22:33 > 14 * Created with HyperLynx version: 7.2 build: 330 > 15 * Design file: CO_X_B1P.tln > 16 * Special Settings: Coupled Lead-Parasitics > 17 > > 18 .TEMP 20.000000 > 19 > > 20 V1003 1003 0 3.3 > 21 V1004 1004 0 0 > 22 V1005 1005 0 5 > 23 V1006 1006 0 5 > 24 V1007 1007 0 5 > 25 V1008 1008 0 5 > 26 V1009 1009 0 5 > 27 V1010 1010 0 5 > 28 V1011 1011 0 5 > 29 V1012 1012 0 0 > 30 VINP 1013 0 PWL 0.0000NS 0.00V 0.0392NS 1.00V > 0.3920NS 1.00V 0.4312NS 0.00V 0.8000NS 0.00V 0.8392NS > 1.00V 1.1920NS 1.00V 1.2312NS 0.00V 1.6000NS 0.00V > 1.6392NS 1.00V 1.9920NS 1.00V 2.0312NS 0.00V 2.4000NS > 0.00V 2.4392NS 1.00V 2.7920NS 1.00V 2.8312NS 0.00V > 3.2000NS 0.00V 3.2392NS 1.00V 3.5920NS 1.00V 3.6312NS > 0.00V 4.0000NS 0.00V 4.0392NS 1.00V 4.3920NS 1.00V > 4.4312NS 0.00V > 31 + 4.8000NS 0.00V 4.8392NS 1.00V 5.1920NS 1.00V > 5.2312NS 0.00V 5.6000NS 0.00V 5.6392NS 1.00V 5.9920NS > 1.00V 6.0312NS 0.00V 6.4000NS 0.00V 6.4392NS 1.00V > 6.7920NS 1.00V 6.8312NS 0.00V 7.2000NS 0.00V 7.2392NS > 1.00V 7.5920NS 1.00V 7.6312NS 0.00V 8.0000NS 0.00V > 8.0392NS 1.00V 8.3920NS 1.00V 8.4312NS 0.00V 8.8000NS > 0.00V 8.8392NS 1.00V 9.1920NS 1.00V 9.2312NS 0.00V > 9.6000NS 0.00V > 32 + 9.6392NS 1.00V 9.9920NS 1.00V 10.0312NS 0.00V > 10.4000NS 0.00V 10.4392NS 1.00V 10.7920NS 1.00V 10.8312NS > 0.00V 11.2000NS 0.00V 11.2392NS 1.00V 11.5920NS 1.00V > 11.6312NS 0.00V 12.0000NS 0.00V 12.0392NS 1.00V 12.3920NS > 1.00V 12.4312NS 0.00V 12.8000NS 0.00V 12.8392NS 1.00V > 13.1920NS 1.00V 13.2312NS 0.00V 13.6000NS 0.00V 13.6392NS > 1.00V 13.9920NS 1.00V 14.0312NS 0.00V 14.4000NS 0.00V > 14.4392NS 1.00V > 33 + 14.7920NS 1.00V 14.8312NS 0.00V 15.2000NS 0.00V > 15.2392NS 1.00V 15.5920NS 1.00V 15.6312NS 0.00V 16.0000NS > 0.00V 16.0392NS 1.00V 16.3920NS 1.00V 16.4312NS 0.00V > 16.8000NS 0.00V 16.8392NS 1.00V 17.1920NS 1.00V 17.2312NS > 0.00V 17.6000NS 0.00V 17.6392NS 1.00V 17.9920NS 1.00V > 18.0312NS 0.00V 18.4000NS 0.00V 18.4392NS 1.00V 18.7920NS > 1.00V 18.8312NS 0.00V 19.2000NS 0.00V 19.2392NS 1.00V > 19.5920NS 1.00V > 34 + 19.6312NS 0.00V 20.0000NS 0.00V 20.0392NS 1.00V > 20.3920NS 1.00V 20.4312NS 0.00V 20.8000NS 0.00V 20.8392NS > 1.00V 21.1920NS 1.00V 21.2312NS 0.00V 21.6000NS 0.00V > 21.6392NS 1.00V 21.9920NS 1.00V 22.0312NS 0.00V 22.4000NS > 0.00V 22.4392NS 1.00V 22.7920NS 1.00V 22.8312NS 0.00V > 23.2000NS 0.00V 23.2392NS 1.00V 23.5920NS 1.00V 23.6312NS > 0.00V 24.0000NS 0.00V 24.0392NS 1.00V 24.3920NS 1.00V > 24.4312NS 0.00V > 35 + 24.8000NS 0.00V 24.8392NS 1.00V 25.1920NS 1.00V > 25.2312NS 0.00V 25.6000NS 0.00V 25.6392NS 1.00V 25.9920NS > 1.00V 26.0312NS 0.00V 26.4000NS 0.00V 26.4392NS 1.00V > 26.7920NS 1.00V 26.8312NS 0.00V 27.2000NS 0.00V 27.2392NS > 1.00V 27.5920NS 1.00V 27.6312NS 0.00V 28.0000NS 0.00V > 28.0392NS 1.00V 28.3920NS 1.00V 28.4312NS 0.00V 28.8000NS > 0.00V 28.8392NS 1.00V 29.1920NS 1.00V 29.2312NS 0.00V > 29.6000NS 0.00V > 36 + 29.6392NS 1.00V 29.9920NS 1.00V 30.0312NS 0.00V > 30.4000NS 0.00V 30.4392NS 1.00V 30.7920NS 1.00V 30.8312NS > 0.00V 31.2000NS 0.00V 31.2392NS 1.00V 31.5920NS 1.00V > 31.6312NS 0.00V 32.0000NS 0.00V 32.0392NS 1.00V 32.3920NS > 1.00V 32.4312NS 0.00V 32.8000NS 0.00V 32.8392NS 1.00V > 33.1920NS 1.00V 33.2312NS 0.00V 33.6000NS 0.00V 33.6392NS > 1.00V 33.9920NS 1.00V 34.0312NS 0.00V 34.4000NS 0.00V > 34.4392NS 1.00V > 37 + 34.7920NS 1.00V 34.8312NS 0.00V 35.2000NS 0.00V > 35.2392NS 1.00V 35.5920NS 1.00V 35.6312NS 0.00V 36.0000NS > 0.00V 36.0392NS 1.00V 36.3920NS 1.00V 36.4312NS 0.00V > 36.8000NS 0.00V 36.8392NS 1.00V 37.1920NS 1.00V 37.2312NS > 0.00V 37.6000NS 0.00V 37.6392NS 1.00V 37.9920NS 1.00V > 38.0312NS 0.00V 38.4000NS 0.00V 38.4392NS 1.00V 38.7920NS > 1.00V 38.8312NS 0.00V 39.2000NS 0.00V 39.2392NS 1.00V > 39.5920NS 1.00V > 38 + 39.6312NS 0.00V 40.0000NS 0.00V 40.0392NS 1.00V > 40.3920NS 1.00V 40.4312NS 0.00V 40.8000NS 0.00V 40.8392NS > 1.00V 41.1920NS 1.00V 41.2312NS 0.00V 41.6000NS 0.00V > 41.6392NS 1.00V 41.9920NS 1.00V 42.0312NS 0.00V 42.4000NS > 0.00V 42.4392NS 1.00V 42.7920NS 1.00V 42.8312NS 0.00V > 43.2000NS 0.00V 43.2392NS 1.00V 43.5920NS 1.00V 43.6312NS > 0.00V 44.0000NS 0.00V 44.0392NS 1.00V 44.3920NS 1.00V > 44.4312NS 0.00V > 39 + 44.8000NS 0.00V 44.8392NS 1.00V 45.1920NS 1.00V > 45.2312NS 0.00V 45.6000NS 0.00V 45.6392NS 1.00V 45.9920NS > 1.00V 46.0312NS 0.00V 46.4000NS 0.00V 46.4392NS 1.00V > 46.7920NS 1.00V 46.8312NS 0.00V 47.2000NS 0.00V 47.2392NS > 1.00V 47.5920NS 1.00V 47.6312NS 0.00V 48.0000NS 0.00V > 48.0392NS 1.00V 48.3920NS 1.00V 48.4312NS 0.00V 48.8000NS > 0.00V 48.8392NS 1.00V 49.1920NS 1.00V 49.2312NS 0.00V > 49.6000NS 0.00V > 40 + 49.6392NS 1.00V 49.9920NS 1.00V 50.0312NS 0.00V > 50.4000NS 0.00V 50.4392NS 1.00V 50.7920NS 1.00V 50.8312NS > 0.00V 51.2000NS 0.00V 51.2392NS 1.00V 51.5920NS 1.00V > 51.6312NS 0.00V 52.0000NS 0.00V 52.0392NS 1.00V 52.3920NS > 1.00V 52.4312NS 0.00V 52.8000NS 0.00V 52.8392NS 1.00V > 53.1920NS 1.00V 53.2312NS 0.00V 53.6000NS 0.00V 53.6392NS > 1.00V 53.9920NS 1.00V 54.0312NS 0.00V 54.4000NS 0.00V > 54.4392NS 1.00V > 41 + 54.7920NS 1.00V 54.8312NS 0.00V 55.2000NS 0.00V > 55.2392NS 1.00V 55.5920NS 1.00V 55.6312NS 0.00V 56.0000NS > 0.00V 56.0392NS 1.00V 56.3920NS 1.00V 56.4312NS 0.00V > 56.8000NS 0.00V 56.8392NS 1.00V 57.1920NS 1.00V 57.2312NS > 0.00V 57.6000NS 0.00V 57.6392NS 1.00V 57.9920NS 1.00V > 58.0312NS 0.00V 58.4000NS 0.00V 58.4392NS 1.00V 58.7920NS > 1.00V 58.8312NS 0.00V 59.2000NS 0.00V 59.2392NS 1.00V > 59.5920NS 1.00V > 42 + 59.6312NS 0.00V 60.0000NS 0.00V 60.0392NS 1.00V > 60.3920NS 1.00V 60.4312NS 0.00V 60.8000NS 0.00V 60.8392NS > 1.00V 61.1920NS 1.00V 61.2312NS 0.00V 61.6000NS 0.00V > 61.6392NS 1.00V 61.9920NS 1.00V 62.0312NS 0.00V 62.4000NS > 0.00V 62.4392NS 1.00V 62.7920NS 1.00V 62.8312NS 0.00V > 63.2000NS 0.00V 63.2392NS 1.00V 63.5920NS 1.00V 63.6312NS > 0.00V 64.0000NS 0.00V 64.0392NS 1.00V 64.3920NS 1.00V > 64.4312NS 0.00V > 43 + 64.8000NS 0.00V 64.8392NS 1.00V 65.1920NS 1.00V > 65.2312NS 0.00V 65.6000NS 0.00V 65.6392NS 1.00V 65.9920NS > 1.00V 66.0312NS 0.00V 66.4000NS 0.00V 66.4392NS 1.00V > 66.7920NS 1.00V 66.8312NS 0.00V 67.2000NS 0.00V 67.2392NS > 1.00V 67.5920NS 1.00V 67.6312NS 0.00V 68.0000NS 0.00V > 68.0392NS 1.00V 68.3920NS 1.00V 68.4312NS 0.00V 68.8000NS > 0.00V 68.8392NS 1.00V 69.1920NS 1.00V 69.2312NS 0.00V > 69.6000NS 0.00V > 44 + 69.6392NS 1.00V 69.9920NS 1.00V 70.0312NS 0.00V > 70.4000NS 0.00V 70.4392NS 1.00V 70.7920NS 1.00V 70.8312NS > 0.00V 71.2000NS 0.00V 71.2392NS 1.00V 71.5920NS 1.00V > 71.6312NS 0.00V 72.0000NS 0.00V 72.0392NS 1.00V 72.3920NS > 1.00V 72.4312NS 0.00V 72.8000NS 0.00V 72.8392NS 1.00V > 73.1920NS 1.00V 73.2312NS 0.00V 73.6000NS 0.00V 73.6392NS > 1.00V 73.9920NS 1.00V 74.0312NS 0.00V 74.4000NS 0.00V > 74.4392NS 1.00V > 45 + 74.7920NS 1.00V 74.8312NS 0.00V 75.2000NS 0.00V > 75.2392NS 1.00V 75.5920NS 1.00V 75.6312NS 0.00V 76.0000NS > 0.00V 76.0392NS 1.00V 76.3920NS 1.00V 76.4312NS 0.00V > 76.8000NS 0.00V 76.8392NS 1.00V 77.1920NS 1.00V 77.2312NS > 0.00V 77.6000NS 0.00V 77.6392NS 1.00V 77.9920NS 1.00V > 78.0312NS 0.00V 78.4000NS 0.00V 78.4392NS 1.00V 78.7920NS > 1.00V 78.8312NS 0.00V 79.2000NS 0.00V 79.2392NS 1.00V > 79.5920NS 1.00V > 46 + 79.6312NS 0.00V 80.0000NS 0.00V 80.0392NS 1.00V > 80.3920NS 1.00V 80.4312NS 0.00V 80.8000NS 0.00V 80.8392NS > 1.00V 81.1920NS 1.00V 81.2312NS 0.00V 81.6000NS 0.00V > 81.6392NS 1.00V 81.9920NS 1.00V 82.0312NS 0.00V 82.4000NS > 0.00V 82.4392NS 1.00V 82.7920NS 1.00V 82.8312NS 0.00V > 83.2000NS 0.00V 83.2392NS 1.00V 83.5920NS 1.00V 83.6312NS > 0.00V 84.0000NS 0.00V 84.0392NS 1.00V 84.3920NS 1.00V > 84.4312NS 0.00V > 47 + 84.8000NS 0.00V 84.8392NS 1.00V 85.1920NS 1.00V > 85.2312NS 0.00V 85.6000NS 0.00V 85.6392NS 1.00V 85.9920NS > 1.00V 86.0312NS 0.00V 86.4000NS 0.00V 86.4392NS 1.00V > 86.7920NS 1.00V 86.8312NS 0.00V 87.2000NS 0.00V 87.2392NS > 1.00V 87.5920NS 1.00V 87.6312NS 0.00V 88.0000NS 0.00V > 88.0392NS 1.00V 88.3920NS 1.00V 88.4312NS 0.00V 88.8000NS > 0.00V 88.8392NS 1.00V 89.1920NS 1.00V 89.2312NS 0.00V > 89.6000NS 0.00V > 48 + 89.6392NS 1.00V 89.9920NS 1.00V 90.0312NS 0.00V > 90.4000NS 0.00V 90.4392NS 1.00V 90.7920NS 1.00V 90.8312NS > 0.00V 91.2000NS 0.00V 91.2392NS 1.00V 91.5920NS 1.00V > 91.6312NS 0.00V 92.0000NS 0.00V 92.0392NS 1.00V 92.3920NS > 1.00V 92.4312NS 0.00V 92.8000NS 0.00V 92.8392NS 1.00V > 93.1920NS 1.00V 93.2312NS 0.00V 93.6000NS 0.00V 93.6392NS > 1.00V 93.9920NS 1.00V 94.0312NS 0.00V 94.4000NS 0.00V > 94.4392NS 1.00V > 49 + 94.7920NS 1.00V 94.8312NS 0.00V 95.2000NS 0.00V > 95.2392NS 1.00V 95.5920NS 1.00V 95.6312NS 0.00V 96.0000NS > 0.00V 96.0392NS 1.00V 96.3920NS 1.00V 96.4312NS 0.00V > 96.8000NS 0.00V 96.8392NS 1.00V 97.1920NS 1.00V 97.2312NS > 0.00V 97.6000NS 0.00V 97.6392NS 1.00V 97.9920NS 1.00V > 98.0312NS 0.00V 98.4000NS 0.00V 98.4392NS 1.00V 98.7920NS > 1.00V 98.8312NS 0.00V 99.2000NS 0.00V 99.2392NS 1.00V > 99.5920NS 1.00V > 50 + 99.6312NS 0.00V > 51 VINN 1014 0 PWL 0.0000NS 1.00V 0.0392NS 0.00V > 0.3920NS 0.00V 0.4312NS 1.00V 0.8000NS 1.00V 0.8392NS > 0.00V 1.1920NS 0.00V 1.2312NS 1.00V 1.6000NS 1.00V > 1.6392NS 0.00V 1.9920NS 0.00V 2.0312NS 1.00V 2.4000NS > 1.00V 2.4392NS 0.00V 2.7920NS 0.00V 2.8312NS 1.00V > 3.2000NS 1.00V 3.2392NS 0.00V 3.5920NS 0.00V 3.6312NS > 1.00V 4.0000NS 1.00V 4.0392NS 0.00V 4.3920NS 0.00V > 4.4312NS 1.00V > 52 + 4.8000NS 1.00V 4.8392NS 0.00V 5.1920NS 0.00V > 5.2312NS 1.00V 5.6000NS 1.00V 5.6392NS 0.00V 5.9920NS > 0.00V 6.0312NS 1.00V 6.4000NS 1.00V 6.4392NS 0.00V > 6.7920NS 0.00V 6.8312NS 1.00V 7.2000NS 1.00V 7.2392NS > 0.00V 7.5920NS 0.00V 7.6312NS 1.00V 8.0000NS 1.00V > 8.0392NS 0.00V 8.3920NS 0.00V 8.4312NS 1.00V 8.8000NS > 1.00V 8.8392NS 0.00V 9.1920NS 0.00V 9.2312NS 1.00V > 9.6000NS 1.00V > 53 + 9.6392NS 0.00V 9.9920NS 0.00V 10.0312NS 1.00V > 10.4000NS 1.00V 10.4392NS 0.00V 10.7920NS 0.00V 10.8312NS > 1.00V 11.2000NS 1.00V 11.2392NS 0.00V 11.5920NS 0.00V > 11.6312NS 1.00V 12.0000NS 1.00V 12.0392NS 0.00V 12.3920NS > 0.00V 12.4312NS 1.00V 12.8000NS 1.00V 12.8392NS 0.00V > 13.1920NS 0.00V 13.2312NS 1.00V 13.6000NS 1.00V 13.6392NS > 0.00V 13.9920NS 0.00V 14.0312NS 1.00V 14.4000NS 1.00V > 14.4392NS 0.00V > 54 + 14.7920NS 0.00V 14.8312NS 1.00V 15.2000NS 1.00V > 15.2392NS 0.00V 15.5920NS 0.00V 15.6312NS 1.00V 16.0000NS > 1.00V 16.0392NS 0.00V 16.3920NS 0.00V 16.4312NS 1.00V > 16.8000NS 1.00V 16.8392NS 0.00V 17.1920NS 0.00V 17.2312NS > 1.00V 17.6000NS 1.00V 17.6392NS 0.00V 17.9920NS 0.00V > 18.0312NS 1.00V 18.4000NS 1.00V 18.4392NS 0.00V 18.7920NS > 0.00V 18.8312NS 1.00V 19.2000NS 1.00V 19.2392NS 0.00V > 19.5920NS 0.00V > 55 + 19.6312NS 1.00V 20.0000NS 1.00V 20.0392NS 0.00V > 20.3920NS 0.00V 20.4312NS 1.00V 20.8000NS 1.00V 20.8392NS > 0.00V 21.1920NS 0.00V 21.2312NS 1.00V 21.6000NS 1.00V > 21.6392NS 0.00V 21.9920NS 0.00V 22.0312NS 1.00V 22.4000NS > 1.00V 22.4392NS 0.00V 22.7920NS 0.00V 22.8312NS 1.00V > 23.2000NS 1.00V 23.2392NS 0.00V 23.5920NS 0.00V 23.6312NS > 1.00V 24.0000NS 1.00V 24.0392NS 0.00V 24.3920NS 0.00V > 24.4312NS 1.00V > 56 + 24.8000NS 1.00V 24.8392NS 0.00V 25.1920NS 0.00V > 25.2312NS 1.00V 25.6000NS 1.00V 25.6392NS 0.00V 25.9920NS > 0.00V 26.0312NS 1.00V 26.4000NS 1.00V 26.4392NS 0.00V > 26.7920NS 0.00V 26.8312NS 1.00V 27.2000NS 1.00V 27.2392NS > 0.00V 27.5920NS 0.00V 27.6312NS 1.00V 28.0000NS 1.00V > 28.0392NS 0.00V 28.3920NS 0.00V 28.4312NS 1.00V 28.8000NS > 1.00V 28.8392NS 0.00V 29.1920NS 0.00V 29.2312NS 1.00V > 29.6000NS 1.00V > 57 + 29.6392NS 0.00V 29.9920NS 0.00V 30.0312NS 1.00V > 30.4000NS 1.00V 30.4392NS 0.00V 30.7920NS 0.00V 30.8312NS > 1.00V 31.2000NS 1.00V 31.2392NS 0.00V 31.5920NS 0.00V > 31.6312NS 1.00V 32.0000NS 1.00V 32.0392NS 0.00V 32.3920NS > 0.00V 32.4312NS 1.00V 32.8000NS 1.00V 32.8392NS 0.00V > 33.1920NS 0.00V 33.2312NS 1.00V 33.6000NS 1.00V 33.6392NS > 0.00V 33.9920NS 0.00V 34.0312NS 1.00V 34.4000NS 1.00V > 34.4392NS 0.00V > 58 + 34.7920NS 0.00V 34.8312NS 1.00V 35.2000NS 1.00V > 35.2392NS 0.00V 35.5920NS 0.00V 35.6312NS 1.00V 36.0000NS > 1.00V 36.0392NS 0.00V 36.3920NS 0.00V 36.4312NS 1.00V > 36.8000NS 1.00V 36.8392NS 0.00V 37.1920NS 0.00V 37.2312NS > 1.00V 37.6000NS 1.00V 37.6392NS 0.00V 37.9920NS 0.00V > 38.0312NS 1.00V 38.4000NS 1.00V 38.4392NS 0.00V 38.7920NS > 0.00V 38.8312NS 1.00V 39.2000NS 1.00V 39.2392NS 0.00V > 39.5920NS 0.00V > 59 + 39.6312NS 1.00V 40.0000NS 1.00V 40.0392NS 0.00V > 40.3920NS 0.00V 40.4312NS 1.00V 40.8000NS 1.00V 40.8392NS > 0.00V 41.1920NS 0.00V 41.2312NS 1.00V 41.6000NS 1.00V > 41.6392NS 0.00V 41.9920NS 0.00V 42.0312NS 1.00V 42.4000NS > 1.00V 42.4392NS 0.00V 42.7920NS 0.00V 42.8312NS 1.00V > 43.2000NS 1.00V 43.2392NS 0.00V 43.5920NS 0.00V 43.6312NS > 1.00V 44.0000NS 1.00V 44.0392NS 0.00V 44.3920NS 0.00V > 44.4312NS 1.00V > 60 + 44.8000NS 1.00V 44.8392NS 0.00V 45.1920NS 0.00V > 45.2312NS 1.00V 45.6000NS 1.00V 45.6392NS 0.00V 45.9920NS > 0.00V 46.0312NS 1.00V 46.4000NS 1.00V 46.4392NS 0.00V > 46.7920NS 0.00V 46.8312NS 1.00V 47.2000NS 1.00V 47.2392NS > 0.00V 47.5920NS 0.00V 47.6312NS 1.00V 48.0000NS 1.00V > 48.0392NS 0.00V 48.3920NS 0.00V 48.4312NS 1.00V 48.8000NS > 1.00V 48.8392NS 0.00V 49.1920NS 0.00V 49.2312NS 1.00V > 49.6000NS 1.00V > 61 + 49.6392NS 0.00V 49.9920NS 0.00V 50.0312NS 1.00V > 50.4000NS 1.00V 50.4392NS 0.00V 50.7920NS 0.00V 50.8312NS > 1.00V 51.2000NS 1.00V 51.2392NS 0.00V 51.5920NS 0.00V > 51.6312NS 1.00V 52.0000NS 1.00V 52.0392NS 0.00V 52.3920NS > 0.00V 52.4312NS 1.00V 52.8000NS 1.00V 52.8392NS 0.00V > 53.1920NS 0.00V 53.2312NS 1.00V 53.6000NS 1.00V 53.6392NS > 0.00V 53.9920NS 0.00V 54.0312NS 1.00V 54.4000NS 1.00V > 54.4392NS 0.00V > 62 + 54.7920NS 0.00V 54.8312NS 1.00V 55.2000NS 1.00V > 55.2392NS 0.00V 55.5920NS 0.00V 55.6312NS 1.00V 56.0000NS > 1.00V 56.0392NS 0.00V 56.3920NS 0.00V 56.4312NS 1.00V > 56.8000NS 1.00V 56.8392NS 0.00V 57.1920NS 0.00V 57.2312NS > 1.00V 57.6000NS 1.00V 57.6392NS 0.00V 57.9920NS 0.00V > 58.0312NS 1.00V 58.4000NS 1.00V 58.4392NS 0.00V 58.7920NS > 0.00V 58.8312NS 1.00V 59.2000NS 1.00V 59.2392NS 0.00V > 59.5920NS 0.00V > 63 + 59.6312NS 1.00V 60.0000NS 1.00V 60.0392NS 0.00V > 60.3920NS 0.00V 60.4312NS 1.00V 60.8000NS 1.00V 60.8392NS > 0.00V 61.1920NS 0.00V 61.2312NS 1.00V 61.6000NS 1.00V > 61.6392NS 0.00V 61.9920NS 0.00V 62.0312NS 1.00V 62.4000NS > 1.00V 62.4392NS 0.00V 62.7920NS 0.00V 62.8312NS 1.00V > 63.2000NS 1.00V 63.2392NS 0.00V 63.5920NS 0.00V 63.6312NS > 1.00V 64.0000NS 1.00V 64.0392NS 0.00V 64.3920NS 0.00V > 64.4312NS 1.00V > 64 + 64.8000NS 1.00V 64.8392NS 0.00V 65.1920NS 0.00V > 65.2312NS 1.00V 65.6000NS 1.00V 65.6392NS 0.00V 65.9920NS > 0.00V 66.0312NS 1.00V 66.4000NS 1.00V 66.4392NS 0.00V > 66.7920NS 0.00V 66.8312NS 1.00V 67.2000NS 1.00V 67.2392NS > 0.00V 67.5920NS 0.00V 67.6312NS 1.00V 68.0000NS 1.00V > 68.0392NS 0.00V 68.3920NS 0.00V 68.4312NS 1.00V 68.8000NS > 1.00V 68.8392NS 0.00V 69.1920NS 0.00V 69.2312NS 1.00V > 69.6000NS 1.00V > 65 + 69.6392NS 0.00V 69.9920NS 0.00V 70.0312NS 1.00V > 70.4000NS 1.00V 70.4392NS 0.00V 70.7920NS 0.00V 70.8312NS > 1.00V 71.2000NS 1.00V 71.2392NS 0.00V 71.5920NS 0.00V > 71.6312NS 1.00V 72.0000NS 1.00V 72.0392NS 0.00V 72.3920NS > 0.00V 72.4312NS 1.00V 72.8000NS 1.00V 72.8392NS 0.00V > 73.1920NS 0.00V 73.2312NS 1.00V 73.6000NS 1.00V 73.6392NS > 0.00V 73.9920NS 0.00V 74.0312NS 1.00V 74.4000NS 1.00V > 74.4392NS 0.00V > 66 + 74.7920NS 0.00V 74.8312NS 1.00V 75.2000NS 1.00V > 75.2392NS 0.00V 75.5920NS 0.00V 75.6312NS 1.00V 76.0000NS > 1.00V 76.0392NS 0.00V 76.3920NS 0.00V 76.4312NS 1.00V > 76.8000NS 1.00V 76.8392NS 0.00V 77.1920NS 0.00V 77.2312NS > 1.00V 77.6000NS 1.00V 77.6392NS 0.00V 77.9920NS 0.00V > 78.0312NS 1.00V 78.4000NS 1.00V 78.4392NS 0.00V 78.7920NS > 0.00V 78.8312NS 1.00V 79.2000NS 1.00V 79.2392NS 0.00V > 79.5920NS 0.00V > 67 + 79.6312NS 1.00V 80.0000NS 1.00V 80.0392NS 0.00V > 80.3920NS 0.00V 80.4312NS 1.00V 80.8000NS 1.00V 80.8392NS > 0.00V 81.1920NS 0.00V 81.2312NS 1.00V 81.6000NS 1.00V > 81.6392NS 0.00V 81.9920NS 0.00V 82.0312NS 1.00V 82.4000NS > 1.00V 82.4392NS 0.00V 82.7920NS 0.00V 82.8312NS 1.00V > 83.2000NS 1.00V 83.2392NS 0.00V 83.5920NS 0.00V 83.6312NS > 1.00V 84.0000NS 1.00V 84.0392NS 0.00V 84.3920NS 0.00V > 84.4312NS 1.00V > 68 + 84.8000NS 1.00V 84.8392NS 0.00V 85.1920NS 0.00V > 85.2312NS 1.00V 85.6000NS 1.00V 85.6392NS 0.00V 85.9920NS > 0.00V 86.0312NS 1.00V 86.4000NS 1.00V 86.4392NS 0.00V > 86.7920NS 0.00V 86.8312NS 1.00V 87.2000NS 1.00V 87.2392NS > 0.00V 87.5920NS 0.00V 87.6312NS 1.00V 88.0000NS 1.00V > 88.0392NS 0.00V 88.3920NS 0.00V 88.4312NS 1.00V 88.8000NS > 1.00V 88.8392NS 0.00V 89.1920NS 0.00V 89.2312NS 1.00V > 89.6000NS 1.00V > 69 + 89.6392NS 0.00V 89.9920NS 0.00V 90.0312NS 1.00V > 90.4000NS 1.00V 90.4392NS 0.00V 90.7920NS 0.00V 90.8312NS > 1.00V 91.2000NS 1.00V 91.2392NS 0.00V 91.5920NS 0.00V > 91.6312NS 1.00V 92.0000NS 1.00V 92.0392NS 0.00V 92.3920NS > 0.00V 92.4312NS 1.00V 92.8000NS 1.00V 92.8392NS 0.00V > 93.1920NS 0.00V 93.2312NS 1.00V 93.6000NS 1.00V 93.6392NS > 0.00V 93.9920NS 0.00V 94.0312NS 1.00V 94.4000NS 1.00V > 94.4392NS 0.00V > 70 + 94.7920NS 0.00V 94.8312NS 1.00V 95.2000NS 1.00V > 95.2392NS 0.00V 95.5920NS 0.00V 95.6312NS 1.00V 96.0000NS > 1.00V 96.0392NS 0.00V 96.3920NS 0.00V 96.4312NS 1.00V > 96.8000NS 1.00V 96.8392NS 0.00V 97.1920NS 0.00V 97.2312NS > 1.00V 97.6000NS 1.00V 97.6392NS 0.00V 97.9920NS 0.00V > 98.0312NS 1.00V 98.4000NS 1.00V 98.4392NS 0.00V 98.7920NS > 0.00V 98.8312NS 1.00V 99.2000NS 1.00V 99.2392NS 0.00V > 99.5920NS 0.00V > 71 + 99.6312NS 1.00V > 72 V001 1002 0 0.0 > 73 X1 1013 1014 1 2 3 4 CO_X_B1P > 74 > > 75 > > 76 > > 77 * Node 1 = S12P1.B5 (driver) Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 78 * Node 2 = S1P2.B7 Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 79 * Node 3 = S12P1.A5 (driver) Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 80 * Node 4 = S1P2.A7 Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 81 > > 82 * Node 0 = Gnd (Common Return) > 83 > > 84 *<<<Spice Models>>> > 85 *.subckt rx_esd_term_N_couple CTD_VDD_15 CTD_VDD_25 CTD_VSS > RXN_in RXN_out > 86 X2 1003 1003 0 NC0 3 NC1 1 1003 NC2 RX_ESD_TERM_N_COUPLE > 87 *.subckt rx_esd_term_N_couple CTD_VDD_15 CTD_VDD_25 CTD_VSS > RXN_in RXN_out > 88 X3 1003 1003 0 4 NC3 2 NC4 1003 NC5 RX_ESD_TERM_N_COUPLE > 89 .OPTIONS SEARCH='D:\' > 90 .OPTIONS SEARCH='D:\MENTOR GRAPHICS\2004\HYPERLYNX\LIBS\' > 91 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO > KIT\SIS_KIT_V2P_V3.6\EXAMPLE\HYP_BP\' > 92 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO > KIT\SIS_KIT_V2P_V3.6\IC_MODELS\ELDO\' > 93 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO > KIT\SIS_KIT_V2P_V3.6\CONNECTOR_MODELS\TERADYNE_HSD\MODELS\' > 94 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO > KIT\SIS_KIT_V2P_V3.6\CONNECTOR_MODELS\TYCO_HSSDC2\MODELS\' > 95 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO > KIT\SIS_KIT_V2P_V3.6\VIA_MODELS\' > 96 .OPTIONS SEARCH='D:\PROJECTS\XALTED\SIMULATION\MODELS\' > 97 .OPTIONS SEARCH='D:\PROJECTS\XALTED\SIMULATION\4X-BPC\' > 98 .OPTIONS SEARCH='D:\CKS_KNOWLEDGE\ROCKET-IO_KIT\SIS_KIT_V2P_V3.6\EXAMPLE\HYP_BP\' > 99 .OPTIONS SEARCH='D:\PROJECTS\NATSEM\SPICE_INFO\NETLIST\' > 100 .OPTIONS SEARCH='D:\PROJECTS\IWAVE\MODELS\' > 101 .OPTIONS SEARCH='D:\PROJECTS\CENTILLIUM\MOTHERBOARD\MODELS\' > 102 ** including D:\rocketio_rx.inc > 1 ************************************************ > 2 ************ Xilinx RocketIO RX ************ > 3 ***************** (start) **************** > 4 ************************************************ > 5 > > 6 .SUBCKT RX_LOOPBACK_TERM CTD_VDD CTD_VSS LBN LBP EN > 25 .ENDS RX_LOOPBACK_TERM > 26 > > 27 ** End of subcircuit definition. > 28 > > 29 .SUBCKT RX_AFE_LOAD2 CTD_VDD CTD_VSS R_2 R_1 R_0 SOURCE > 48 .ENDS RX_AFE_LOAD2 > 49 > > 50 ** End of subcircuit definition. > 51 > > 52 .SUBCKT RX_AFE_LOAD1 CTD_VDD CTD_VSS LB RA_1 RA_0 RB_1 RB_0 > SOURCE > 108 .ENDS RX_AFE_LOAD1 > 109 > > 110 ** End of subcircuit definition. > 111 > > 112 .SUBCKT RX_AFE_R1 CTD_VDD CTD_VSS IN_100U_LB LB LBN LBP OUTN > OUTP PD RDN > 113 + RDP RX_FE_I_1 RX_FE_I_0 RX_FE_R_9 RX_FE_R_8 RX_FE_R_7 > RX_FE_R_6 > 114 + RX_FE_R_5 RX_FE_R_4 RX_FE_R_3 RX_FE_R_2 RX_FE_R_1 RX_FE_R_0 > 170 .ENDS RX_AFE_R1 > 171 > > 172 ** End of subcircuit definition. > 173 > > 174 .SUBCKT RX_AC_CAP P1 P2 > 9 .ENDS RX_AC_CAP > 10 > > 11 ** End of subcircuit definition. > 12 > > 13 .SUBCKT RX_1M_R CTD_VDD TERM1 TERM2 > 68 .ENDS RX_1M_R > 69 > > 70 ** End of subcircuit definition. > 71 > > 72 .SUBCKT RX_AC_R CTD_VDD IPULSE_1 IPULSE_2 VREF > 10 .ENDS RX_AC_R > 11 > > 12 ** End of subcircuit definition. > 13 > > 14 .SUBCKT RX_ESD_TERM_N_COUPLE CTD_VDD_15 CTD_VDD_25 CTD_VSS > RXN_IN RXN_OUT > 15 + RXP_IN RXP_OUT VTRX VREF > 56 .ENDS RX_ESD_TERM_N_COUPLE > 57 > > 58 ** End of subcircuit definition. > 59 > > 60 .SUBCKT RX CTD_VDD_15 CTD_VDD_25 DATA_N DATA_P LB_N LB_P RXN > RXP > 61 + RX_GND VTRX LOOPBACK_1 PD RX_FE_I_1 RX_FE_I_0 RX_FE_R_9 > RX_FE_R_8 > 62 + RX_FE_R_7 RX_FE_R_6 RX_FE_R_5 RX_FE_R_4 RX_FE_R_3 RX_FE_R_2 > 63 + RX_FE_R_1 RX_FE_R_0 VREF_AFE > 59 .ENDS RX > 60 > > 61 ** End of subcircuit definition. > 62 > > 63 > > 64 ************************************************ > 65 ************ Xilinx RocketIO RX ************ > 66 ****************** (end) ***************** > 67 ************************************************ > 68 > > 102 > 103 *<<<End Spice Models>>> > 104 > > 105 > > 106 ** including D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp > 1 * Netlist for net Lsw00 - > D:\PROJECTS\XALTED\SIMULATION\XLS-20\CO_X_B1P.sp > 2 > > 3 > > 4 * Output from HyperLynx SPICE Writer > 5 * Created by CG-CoreEl on Date: Monday Oct. 11,2004 Time: > 21:22:33 > 6 * Created with HyperLynx version: 7.2 build: 330 > 7 * Design file: CO_X_B1P.tln > 8 * Special Settings: Coupled Lead-Parasitics > 9 > > 10 > > 11 .SUBCKT CO_X_B1P VINP VINN 101 111 114 124 > 12 > > 13 * Node # = <Reference Designator>.<pin name> > 14 ********************************************** > 15 * Node 101 = S12P1.B5 (driver) Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 16 * Node 111 = S1P2.B7 Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 17 * Node 114 = S12P1.A5 (driver) Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 18 * Node 124 = S1P2.A7 Library=rocketio_rx.inc > model=rx_esd_term_N_couple > 19 > > 20 * Node 0 = Gnd (Common Return) > 21 > > 22 > > 23 T001 101 0 103 0 Z0=5.800000E+001 > TD=2.000000E-010 > 24 W002 N=1 103 0 104 0 RLGCmodel=Model_W002 > L=0.00369267 MULTIDEBYE=1 > 25 W008 N=1 109 0 111 0 RLGCmodel=Model_W008 > L=0.0165475 MULTIDEBYE=1 > 26 T009 114 0 116 0 Z0=5.800000E+001 > TD=2.000000E-010 > 27 W010 N=1 116 0 117 0 RLGCmodel=Model_W010 > L=0.00147276 MULTIDEBYE=1 > 28 W016 N=1 122 0 124 0 RLGCmodel=Model_W016 > L=0.019668 MULTIDEBYE=1 > 29 > > 30 WCOND_000 121 108 0 122 109 0 RLGCmodel=Cond_000 N=2 > L=0.008352 MULTIDEBYE=1 > 31 WCOND_001 120 107 0 121 108 0 RLGCmodel=Cond_001 N=2 > L=0.023949 MULTIDEBYE=1 > 32 WCOND_002 119 106 0 120 107 0 RLGCmodel=Cond_002 N=2 > L=0.210226 MULTIDEBYE=1 > 33 WCOND_003 105 118 0 106 119 0 RLGCmodel=Cond_003 N=2 > L=0.011608 MULTIDEBYE=1 > 34 WCOND_004 117 104 0 118 105 0 RLGCmodel=Cond_004 N=2 > L=0.013277 MULTIDEBYE=1 > 35 V1 1 0 0.00 > 36 **** Transmission line models *********************** > 37 > > 38 ********************************* > 39 * Single uncoupled transmission line > 40 > > 41 .MODEL MODEL_W002 W MODELTYPE=RLGC N=1 > 42 * Lo (H/m) > 43 + LO = > 44 + 3.59892E-007 > 45 > > 46 * Co (F/m) > 47 + CO = > 48 + 1.39123E-010 > 49 > > 50 * Ro (Ohm/m) > 51 + RO = > 52 + 4.4911 > 53 > > 54 * Go (S/m) > 55 + GO = > 56 + 0 > 57 > > 58 * Rs (Ohm/m-sqrt(Hz)) > 59 + RS = > 60 + 0.000578602 > 61 > > 62 * Gd (S/m-Hz) > 63 + GD = > 64 + 2.78246E-012 > 65 > > 66 > > 67 ********************************* > 68 * Single uncoupled transmission line > 69 > > 70 .MODEL MODEL_W008 W MODELTYPE=RLGC N=1 > 71 * Lo (H/m) > 72 + LO = > 73 + 3.59892E-007 > 74 > > 75 * Co (F/m) > 76 + CO = > 77 + 1.39123E-010 > 78 > > 79 * Ro (Ohm/m) > 80 + RO = > 81 + 4.4911 > 82 > > 83 * Go (S/m) > 84 + GO = > 85 + 0 > 86 > > 87 * Rs (Ohm/m-sqrt(Hz)) > 88 + RS = > 89 + 0.000578602 > 90 > > 91 * Gd (S/m-Hz) > 92 + GD = > 93 + 2.78246E-012 > 94 > > 95 > > 96 ********************************* > 97 * Single uncoupled transmission line > 98 > > 99 .MODEL MODEL_W010 W MODELTYPE=RLGC N=1 > 100 * Lo (H/m) > 101 + LO = > 102 + 3.59892E-007 > 103 > > 104 * Co (F/m) > 105 + CO = > 106 + 1.39123E-010 > 107 > > 108 * Ro (Ohm/m) > 109 + RO = > 110 + 4.4911 > 111 > > 112 * Go (S/m) > 113 + GO = > 114 + 0 > 115 > > 116 * Rs (Ohm/m-sqrt(Hz)) > 117 + RS = > 118 + 0.000578602 > 119 > > 120 * Gd (S/m-Hz) > 121 + GD = > 122 + 2.78246E-012 > 123 > > 124 > > 125 ********************************* > 126 * Single uncoupled transmission line > 127 > > 128 .MODEL MODEL_W016 W MODELTYPE=RLGC N=1 > 129 * Lo (H/m) > 130 + LO = > 131 + 3.59892E-007 > 132 > > 133 * Co (F/m) > 134 + CO = > 135 + 1.39123E-010 > 136 > > 137 * Ro (Ohm/m) > 138 + RO = > 139 + 4.4911 > 140 > > 141 * Go (S/m) > 142 + GO = > 143 + 0 > 144 > > 145 * Rs (Ohm/m-sqrt(Hz)) > 146 + RS = > 147 + 0.000578602 > 148 > > 149 * Gd (S/m-Hz) > 150 + GD = > 151 + 2.78246E-012 > 152 > > 153 ********************************* > 154 * RLGC model created by HyperLynx SPICE generator > 155 * > 156 .MODEL COND_000 W MODELTYPE=RLGC N=2 > 157 * Lo (H/m) > 158 + LO = > 159 + 3.5972E-007 > 160 + 2.63282E-008 3.5972E-007 > 161 > > 162 * Co (F/m) > 163 + CO = > 164 + 1.39939E-010 > 165 + -1.02423E-011 1.39939E-010 > 166 > > 167 * Ro (Ohm/m) > 168 + RO = > 169 + 4.4911 > 170 + 0 4.4911 > 171 > > 172 * Go (S/m) > 173 + GO = > 174 + 0 > 175 + 0 0 > 176 > > 177 * Rs (Ohm/m-sqrt(Hz)) > 178 + RS = > 179 + 0.00106555 > 180 + 2.10618E-005 0.00106555 > 181 > > 182 * Gd (S/m-Hz) > 183 + GD = > 184 + 1.75853E-011 > 185 + -1.28708E-012 1.75853E-011 > 186 > > 187 ********************************* > 188 > > 189 ********************************* > 190 * RLGC model created by HyperLynx SPICE generator > 191 * > 192 .MODEL COND_001 W MODELTYPE=RLGC N=2 > 193 * Lo (H/m) > 194 + LO = > 195 + 3.5972E-007 > 196 + 2.63128E-008 3.5972E-007 > 197 > > 198 * Co (F/m) > 199 + CO = > 200 + 1.39938E-010 > 201 + -1.02362E-011 1.39938E-010 > 202 > > 203 * Ro (Ohm/m) > 204 + RO = > 205 + 4.4911 > 206 + 0 4.4911 > 207 > > 208 * Go (S/m) > 209 + GO = > 210 + 0 > 211 + 0 0 > 212 > > 213 * Rs (Ohm/m-sqrt(Hz)) > 214 + RS = > 215 + 0.00106552 > 216 + 2.10544E-005 0.00106552 > 217 > > 218 * Gd (S/m-Hz) > 219 + GD = > 220 + 1.75852E-011 > 221 + -1.28632E-012 1.75852E-011 > 222 > > 223 ********************************* > 224 > > 225 ********************************* > 226 * RLGC model created by HyperLynx SPICE generator > 227 * > 228 .MODEL COND_002 W MODELTYPE=RLGC N=2 > 229 * Lo (H/m) > 230 + LO = > 231 + 3.5972E-007 > 232 + 2.63282E-008 3.5972E-007 > 233 > > 234 * Co (F/m) > 235 + CO = > 236 + 1.39939E-010 > 237 + -1.02423E-011 1.39939E-010 > 238 > > 239 * Ro (Ohm/m) > 240 + RO = > 241 + 4.4911 > 242 + 0 4.4911 > 243 > > 244 * Go (S/m) > 245 + GO = > 246 + 0 > 247 + 0 0 > 248 > > 249 * Rs (Ohm/m-sqrt(Hz)) > 250 + RS = > 251 + 0.00106555 > 252 + 2.10618E-005 0.00106555 > 253 > > 254 * Gd (S/m-Hz) > 255 + GD = > 256 + 1.75853E-011 > 257 + -1.28708E-012 1.75853E-011 > 258 > > 259 ********************************* > 260 > > 261 ********************************* > 262 * RLGC model created by HyperLynx SPICE generator > 263 * > 264 .MODEL COND_003 W MODELTYPE=RLGC N=2 > 265 * Lo (H/m) > 266 + LO = > 267 + 3.5972E-007 > 268 + 2.63282E-008 3.5972E-007 > 269 > > 270 * Co (F/m) > 271 + CO = > 272 + 1.39939E-010 > 273 + -1.02423E-011 1.39939E-010 > 274 > > 275 * Ro (Ohm/m) > 276 + RO = > 277 + 4.4911 > 278 + 0 4.4911 > 279 > > 280 * Go (S/m) > 281 + GO = > 282 + 0 > 283 + 0 0 > 284 > > 285 * Rs (Ohm/m-sqrt(Hz)) > 286 + RS = > 287 + 0.00106555 > 288 + 2.10618E-005 0.00106555 > 289 > > 290 * Gd (S/m-Hz) > 291 + GD = > 292 + 1.75853E-011 > 293 + -1.28708E-012 1.75853E-011 > 294 > > 295 ********************************* > 296 > > 297 ********************************* > 298 * RLGC model created by HyperLynx SPICE generator > 299 * > 300 .MODEL COND_004 W MODELTYPE=RLGC N=2 > 301 * Lo (H/m) > 302 + LO = > 303 + 3.5972E-007 > 304 + 2.63282E-008 3.5972E-007 > 305 > > 306 * Co (F/m) > 307 + CO = > 308 + 1.39939E-010 > 309 + -1.02423E-011 1.39939E-010 > 310 > > 311 * Ro (Ohm/m) > 312 + RO = > 313 + 4.4911 > 314 + 0 4.4911 > 315 > > 316 * Go (S/m) > 317 + GO = > 318 + 0 > 319 + 0 0 > 320 > > 321 * Rs (Ohm/m-sqrt(Hz)) > 322 + RS = > 323 + 0.00106555 > 324 + 2.10618E-005 0.00106555 > 325 > > 326 * Gd (S/m-Hz) > 327 + GD = > 328 + 1.75853E-011 > 329 + -1.28708E-012 1.75853E-011 > 330 > > 331 ********************************* > 332 > > 333 > > 334 **** End Transmission line models ******************* > 335 > > 336 .ENDS > 106 > 107 > > 108 *<<<Scope Time>>> > 109 .TRAN 5.2PS 100.02NS > 110 .OPTION step=5.2e-012 > 111 > > 112 > > 113 *** Start inclusions > 114 *** End inclusions > 115 > > 116 .PRINT TRAN V(3 ) > 117 V126 3 126 0.0 > 118 .PRINT TRAN V(1 ) > 119 V127 1 127 0.0 > 120 > > 121 .END > > End of file > > > ***** 0 error(s). > ***** 0 warning(s). > > ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_VDDCDM": > Undeclared subcircuit reference. > Instance appeared near source line 14 > ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_VSSCDM": > Undeclared subcircuit reference. > Instance appeared near source line 14 > ERROR 702: SUBCKT "RX_1M_R.ANA_RPPO1RPOP": Undeclared subcircuit > reference. > Instance appeared near source line 12 > ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.XMN_ESDDIODE_HBM": Undeclared > subcircuit reference. > Instance appeared near source line 14 > ERROR 702: SUBCKT "RX_ESD_TERM_N_COUPLE.ANA_RPPO1RPOP": Undeclared > subcircuit reference. > Instance appeared near source line 14 > > > ***** GENERATION ... > > > ***** 5 error(s). > ***** 0 warning(s). > > > INFORMATION ABOUT COMPILATION > > > Memory space allocated (bytes): 551274 > 0 elements > 0 nodes > 0 input signals > > Check your input netlist... > > > Job started at 11-Oct-2004 21:22:33 > Job end at 11-Oct-2004 21:22:34 > > Run on Win

I am looking for an eval board for the XC2V6000 in the 1517 package that has a socket for the BGA devices. The reason I need this board is to test a number of devices I have just recieved back that have been re-balled. Xilinx has a similar eval board available on their website but it only supports the 1152 pin package. There is mention of adapter cards that support other device packages but I can't seem to find additional information. Any help and or direction would be greatly aprreciated

"colin" <colin_toogood@yahoo.com> wrote in message news:885a4a4a.0410130836.783072db@posting.google.com... > Hi > > Does anyone know the cheapest way to generate the 1.2V needed for > spartan3. All the linear regs that say they go down to 1.2 have a vref > that is 1.2 to 1.3V. All I can think is that the leakage on the adj > pin when it is grounded makes some difference or that 1.2 is the > marketing b*ll. > > Colin Do you not believe that the linear regulators that supply sub-1.245V are producing the results you see in the data sheet graphs? After a 12 second search, the $0.19 National LMS5258 is limited to 150mA (you didn't specify your current needs or your Spartan-3 size) but has full documentation on current versus voltage. You should be able to find many devices out there that fit your needs, whatever they may happen to be.

Colin, It's hard to answer this question without knowing what the FPGA is doing. If the I/Os are switching slowly, but the logic inside is going very fast, then your Vccint supply is of paramount importance. For example, if all the slew rates in the IOBs are set to slow, the 3.3V rail maybe doesn't need to be on a plane. In fact a crappy Vcco can sometimes actually help EMI problems by slowing the IO signals. I'd say that as you're using a PQ208, high speed stuff isn't foremost in your mind. When Xilinx say that 'all the supplies are recommended to be on a plane', what I guess they mean is 'we tried it with all the supplies on a plane and it met ALL our specs'. They're not saying other methodologies won't work, especially if you're not trying to meet the fastest switching rates. Although wire-wrap's probably a bad idea! What you can do is what I think you're suggesting, have mini-planes for each supply, sharing the PCB layer. If you can also get some 0402 caps on the top-side (fpga-side) of the board very close to the pins, that'll help a lot. With the package you're using just go for the biggest value X5R cap you can get, 1uF probably, and route it on the top layer straight to the pins. This takes the via inductance out of the equation. Don't worry about all that 'use several different values to widen the resonance', that's probably mumbo-jumbo in the real world, especially with a PQ208. There are too many parasitics around to confuse the issue. Small package (=low inductance), big capacitance is what you want! The point-of-load supplies Austin mentions are a good idea, but don't bust a gut getting them close to the FPGA, just make sure the supply rails have very low AC impedance near the FPGA. So, lots of point-of-load decoupling and lots of copper is what you need! If I were you, I'd be optimistic. You're thinking about this, which gives you a much, much higher chance of success than some folks... Good luck, Syms. p.s. More reading:- http://www.sigcon.com/pubsIndex.htm Look at 'Bypass Capacitors'. "colin" <colin_toogood@yahoo.com> wrote in message news:885a4a4a.0410130035.45941216@posting.google.com... > Hi guys > > I have just finished routing a simple board with a 208 pin qfp spartan > 3. I have just used top and bottom layers and it is time to add the > power. I need 3.3v for all IO and the 1.2v and 2.5v for vccint and > vccaux. I have not routed any signal under the spartan on either layer > so I plan to use GND on 1 inner layer and 3.3 on the fourth layer with > an island of 1.2 or 2.5 under the spartan with 2.5 or 1.2 then on the > bottom layer. > > Just wondering if anyone can see any holes in this idea. > > thanks > > colin

Arash Salarian wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:416CB979.EC57FD01@yahoo.com... > > I looked at the Altium site and did not find the Spartan 3 modules you > > describe. Did you get this info directly from the sales people? > > > No, I found the information in the altium website. It seems they have just > recently modified the evaluation package and now offer it with Spartan 3. > Here is the online order form with the part number of the FPGAs on board. > http://www.altium.com/evaluation/ > It seems that the original offer included BOTH Xilinx and Altera's FPGAs (in > the form of daugther boards) but the new one comes separately. I found the offer, but I can't find any info on what the board is... I don't use Flash and I am not willing to download an exe file. Don't they even have a data sheet??? As someone else pointed out, they are selling this board as a way to evaluate their software. So I am not clear about what I can do with it without buying their software. I also would like to know more about the IO capabilities. I sort of doubt that a Flash presentation will give me much technical info. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

I believe that you need to map the simprim library name to where you compiled the simprim models. There are many ways to do this. One way is go to the modelsim.ini that your design process is using. It may be in a project specific path, or a global one. I do not know what method you are using. In modelsim.ini, under [library] add : simprim = "your path name" e.g. simprim = G:/ModelsimLibs/xilinx6_2sp3_PE8_3c/simprim Hope this helps. Newman yaseenzaidi@NETZERO.com (Yaseen Zaidi) wrote in message news:<a31921fc.0410130226.f1d4c03@posting.google.com>... > I generate a testbench and then do Simulate Post-Translate VHDL Model > in ISE 6.2.03i. Modelsim frowns as follow: > > # ** Error: (vcom-19) Failed to access library 'simprim' at "simprim". > # No such file or directory. (errno = ENOENT) > # ** Error: rcvr_translate.vhd(18): Library simprim not found. > # ** Error: rcvr_translate.vhd(19): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(20): Unknown identifier 'simprim'. > # ** Error: rcvr_translate.vhd(22): VHDL Compiler exiting > # ** Error: C:/Modeltech_5.8d/win32/vcom failed. > > I have compiled both simprim and unisim libraries in $Xilinx > directory. The testbench includes the following headers: > > library SIMPRIM; > use SIMPRIM.VCOMPONENTS.ALL; > use SIMPRIM.VPACKAGE.ALL; > > I like to do post translate/map/PAR timing simulation if I could only > get pass this error. > > Thanks, > > YZ

Markus, IIRC, the I2C spec calls for hystersis on the SCL input. The slow rise time as someone else already pointed out, may be creating oscillations after the SCL is buffered into the FPGA via the IOB. One way to verify this is to bring out a test point from after the IOB buffer, and look at it with a scope. If the design is using the buffered SCL clock to clock in data, you may consider "filtering" the glitchy buffered SCL signal to create a clock enable with a (much) faster free running clock if one is available, and using the clock enable along with the free running clock to run the I2C logic. Hope this helps. Newman "Markus Fuchs" <m.fuchs@fplusp.com> wrote in message news:<ckh5us$v46$03$1@news.t-online.com>... > rickman wrote: > > I believe when you say "4,7V" you mean what we call 4.7 volts in the US, > > no? > > Damn, just gave myself away! <grin> > English is not my native language, but you're right: I meant 4.7 volts. > > Jim Granville wrote: > > If the PIC is always the master, you could try making the SCL line > > always CMOS drive : In single master, only SDA needs to be open drain. > > I already tried that without success. > > > That will ensure faster clock edges - what you describe is a > > little counter-intuitive, esp as you say the resistor change had > > no effect, but sounds closest to edge-effects. > > FPGAs tend to be slow edge intolerant. > > Thank you Jim, that was it! I put a buffer between the PIC and the FPGA on > the SCL line and now it works. > So, what do you, Jim, Rick and all the other experts, recommend to get the > edges on the I2C lines faster? > There must be another solution for it, I guess, since buffers won't work on > bidir lines. > > Thank you! > Markus > > PS: Microchip says max. rise/fall time for the I2C lines are 300ns! :-(

Rickman, Just for my own edification, why do you prefer to convert rather than cast. Do you consider it bad style, not portable, personnel preference? I recently transitioned to using numeric_std, and it appeared to me that casting looked more readable when going from std_logic_vector to unsigned and then back to std_logic_vector. It simulated and synthesized without problems, although I have to admit that I did not look at the gate level netlist. Do you think I am missing something? Thanks, Newman "kofeyok" <lomtik@gmail.com> wrote in message news:<8742cebfcf499980dba16f72a2982be3@localhost.talkaboutelectronicequipment.com>... > Thanks for the reply rickman. > > That makes sence now. > I see that passing of values between modules is done using slv.. but you > can can convert (not cast) inside of each module. The signed port gives > non-synthesizable code. At least my simulator refuses to simulate. > > Thanks

Is using the JTAG cable the only way to program the Spartan II on the Avnet Virtex 2 Pro Dev. Kit? I looked into the possibility of using the System ACE or the PCI bus to load the program. From what I gathered, we can only program the V2P from System ACE and for the PCI to work, we need to load the bridge program on the Spartan. Anybody using these boards, please respond. Thanks, Sirish Kondi

newman wrote: > > Rickman, > Just for my own edification, why do you prefer to convert rather > than cast. > Do you consider it bad style, not portable, personnel preference? I > recently transitioned to using numeric_std, and it appeared to me that > casting looked more readable when going from std_logic_vector to > unsigned and then back to std_logic_vector. It simulated and > synthesized without problems, although I have to admit that I did not > look at the gate level netlist. Do you think I am missing something? > > Thanks, > Newman > > "kofeyok" <lomtik@gmail.com> wrote in message news:<8742cebfcf499980dba16f72a2982be3@localhost.talkaboutelectronicequipment.com>... > > Thanks for the reply rickman. > > > > That makes sence now. > > I see that passing of values between modules is done using slv.. but you > > can can convert (not cast) inside of each module. The signed port gives > > non-synthesizable code. At least my simulator refuses to simulate. > > > > Thanks I struggled a bit learning VHDL, mainly with the strong typing and how to get around it. I found that casting could not be used in all cases, and I am still not clear exactly what it does. For example, I am pretty sure you can not cast an integer to an SLV. Conversion, on the other hand, is done with functions written in VHDL. Conversion functions are well defined, normally the source is available and I can even write my own. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX

Rickman, I looked up type conversion in Ashenden's 2'nd edition (page 49), and that is what I did. I think I just misinterpreted what was meant by convert and cast in your message. Newman rickman <spamgoeshere4@yahoo.com> wrote in message news:<4148B147.37214810@yahoo.com>... > kofeyok wrote: > > > > Hi everyone, > > I am fairly new to VHDL and had several questions about types conversions > > that I've numbered for easiness of separating them. Any help would be > > greatly appreciated. > > > > I am using signed type throughout my program. Now, there is one third > > party function that outputs std_logic_vector, that I have to use. The > > function looks like its std_logic_vector signal is in signed format (the > > sine wave with positive and negative values). 1. Can I just assume that > > it's in 2's compliment format similar to signed? In other words, how does > > STD_LOGIC_VECTOR holds signed numbers? > > > > 2. I understand that if I would like to match it to my internal signals, I > > would have to cast that signal to SIGNED. So, can I do > > SIGNED(STD_LOGIC_VECTOR signal) to do that? What would be the result of > > the above statement? Would it take the signal inside and convert it to 2's > > comliment? That would be useless for me if the signal is already in 2's > > compliment. If that's not correct, please let me know how can go around > > this. > > > > 3. I suppose STD_LOGIC_VECTOR can hold any format (1's, 2's or just > > magnitude) as long as you keep in mind in which context you are using it. > > However, the moment you start using SIGNED function, how does VHDL > > compiler recognize the numbers from then? Does it still treat them as > > STD_LOGIC_VECTOR and 'makes a note' for itself that it contains 2's > > compliement? > > > > 4. I've read that ieee.std_logic_arith and ieee.numeric_std are mutually > > exclusive libraries that you cannot use at the same time. Maybe using one > > or another one would somehow answer my questions above.. > > I understand your confusion. Types and type conversion is possibly the > hardest part of learning VHDL. I can't say I am an expert, but I have > written many apps in VHDL and I think I have a handle on this. > std_logic_vector (slv) makes no assumptions about the data that is being > conveyed by the type. The ieee.numeric_std library defines a signed and > unsigned type that support vectors of std_logic, but *do* make > assumptions of the type of numbers they are being used to represent. > Otherwise, I believe these three types are the same. > > This makes a difference only when you are doing operations that rely on > the nature of the number type. If you are just calculating parity, then > you don't care if it is signed or unsigned. My recommendation is to > convert (not cast) the type when you need to change it. This will be > supported by the ieee.numeric_std library for most conversions you will > want to do. to_signed() will convert an slv to a signed type. > TO_STDLOGICVECTOR() will convert back. I believe I am using a custom > package to convert using "to_slv" possibly just because it is less > typing, but I believe I can convert directly from integer to slv. Check > the description of your library. > > The ieee.std_logic_arith is not an IEEE library at all. Likewise with > IEEE.STD_LOGIC_UNSIGNED and IEEE.STD_LOGIC_SIGNED. Worst of all, the > unsigned and signed libraries are mutually exclusive unless you > explicitly identify which library you are using on each conversion > function. So you can't use both signed and unsigned types in the same > program without difficulty. I suggest that you stay away from these. > Below are the common libraries I use. > > Library ieee; > Use ieee.std_logic_1164.all; > Use ieee.numeric_std.all; > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX

hi i have the following question: i'm using a spartan 3 and was wondering if it is possible to set an io pin to tristate. is this possible by using the following vhdl command " IOPin <= 'Z'; " ? thanks urban

"Urban Stadler" <u.stadler@pfeilheim.sth.ac.at> schrieb im Newsbeitrag news:416da060$0$8024$3b214f66@usenet.univie.ac.at... > hi > > i have the following question: > > i'm using a spartan 3 and was wondering if it is possible to set an io pin > to tristate. > is this possible by using the following vhdl command " IOPin <= 'Z'; " ? Yes. Regards Falk

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