Since Apple switched to Intel chips in the mid-00s, the PowerPC chips from Motorola and the PowerPC Instruction Set Architecture (ISA) that they had been using largely fell by the wayside. While true that niche applications like supercomputing still use the Power ISA on other non-Apple hardware, the days of personal computing with PowerPC are largely gone unless you’re still desperately trying to keep your Power Mac G5 out of the landfill or replaying Twilight Princess. Luckily for enthusiasts, though, the Power ISA is now open source and this group has been working on an open-source laptop based on this architecture.
While development is ongoing and there are no end-user products available yet, the progress that this group has made shows promise. They have completed their PCB designs and schematics and have a working bill of materials, including a chassis from Slimbook. There are also prototypes with a T2080RDB development kit and a NXP T2080 processor, although they aren’t running on their intended hardware yet. While still in the infancy, there are promising videos (linked below) which show the prototypes operating smoothly under the auspices of the Debian distribution that is tailored specifically for the Power ISA.
We are excited to see work continue on this project, as the Power ISA has a number of advantages over x86 in performance, ARM when considering that it’s non-proprietary, and even RISC-V since it is older and better understood. If you want a deeper comparison between all of these ISAs, our own [Maya Posch] covered that topic in detail as well as covered the original move that IBM made to open-source the Power ISA.
There is even a group developing a libre SOC based on Open Power PC ISA: https://libre-soc.org/
Interesting reads!
Thanks,
That “flip” from RV64GC RISC-V over to the Power ISA is unexpected, until you see why. ( ref: https://www.crowdsupply.com/libre-risc-v/m-class/updates/nlnet-grants-approved-power-isa-under-consideration ).
And use of 55 year old advancements from Seymour Cray’s CDC 6600, overlooked by Intel and ARM is fascinating.
Yes, I have been reading the book they have unearthed, it has been a fascinating read!
phil, thanks. we couldn’t have understood it without mitch alsup’s help. the augmentations that provide precise exceptions and will also document multi-issue are here: https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
if you already understand the tomasulo algorithm there is a link on there which describes how to do a toplogical transformation into 6600, after which adding multi-issue is an O(N) linear addition. (adding multi-issue to tomasulo is at least quadratic)
Hello Luke, and thank you for everything you and the team are doing on this project. I have been following it since its early days and very much appreciate the work you are sharing, mostly out of pure curiosity (I am an R&D dry-etch engineer so, no hardware designer :) ). I have read most of the material on your website but haven’t joined any mailing list yet (will do). I am looking forward reading more from you guys!
I would love it if the team could work some sort of support for transactional semantics into their implementation, even if it was something simplistic with the granularity of a L1 cache line. Optimistic concurrency is the future for efficient multiprocessing and the recent IBM Powers have some hardware support for it, as do some Xeons.
nes, hi,
we have ah one heck of a lot to do! in particular, we know that GPU workloads tend to eat L1 data caches. they are typically LOAD PROCESS STORE with negligeable overlap in for example texturisation where the maps are hundreds of megabytes.
a typical CPU workload on the other hand is an average of 30% referral to previously loaded data. L1 caches actually get used.
we may therefore need to “lock” or restrict a certain amount of the L1 cache so that GPU workloads do not flush data out completely.
if you have any suggestions please do join the mailing list.
thank you!
incredible. Have a idea? get linux on processor and make a new product.
Great. Great enginier, great linux programmer, great open source
P.S. I’m waiting for laptop with gcc and run 7 days in one charging
How could nobody mention Raptor Computing Systems and the POWER9 based desktop systems they sell?
They range from 4 cores, 16 threads all the way to 22 cores, 88 threads, times two sockets.
All the systems have PCIe 4.0
https://www.raptorcs.com/
They’re based in the USA and while they use CPUs from IBM, they put a LOT of effort into being user-trustable.
They publish all of the source code for their firmware, including firmware inside the CPU that AMD or Intel don’t even admit exists.
https://wiki.raptorcs.com/wiki/OpenPOWER_Firmware
Got me wondering what all lab test equipment used the PowerPC, like the Tektronix TDS-8000’s?
Looks quite interesting – but, of course, the T2080 is an embedded chip like most of the ARM SoCs.
So how does the performance of the T2080 (4 x PPC e6500@1.8 GHz, dual-threaded) compare to the RK3399 in the Pinebook Pro (Big/little 2 x Cortex-A72@2 GHz + 4 x Cortex-A53@1.5 GHz), the i.MX8M in the MNT Reform (4 x Cortex-A53@1.5 GHz) or the BCM2711 in the Raspberry Pi 4 (4 x Cortex-A72@1.5 GHz)?
It would also be interesting to know if the T2080 can address more than 4 GB of physical RAM (a limitation of at least the RK3399 and the BCM2711).
Oh, and… does it run AIX? :-)
NXP T2080 have 40-bit address support, up to 1 TB memory
BCM2711 could address up to 16 GiB (ref: https://hackaday.com/2020/05/28/raspberry-pi-4-gets-its-8-gigs/ )
This ought to get the Amiga weirdos’ blood boiling.
If it runs morphos.
I hope this encourages more people to maintain ppc packages on debian etc.
What’s this going to cost? Will it be in any way comparable in cost to normal x86 laptops or will it be super-expensive like some of the “big iron” PowerPC systems out there?
And just how open will it be (will it still need binary blobs or will it be open right down to the firmware level?)