Designing a computer from scratch is one of the holy grails of hardware design. For programmable logic, designing your own processor is a huge accomplishment. That’s exactly what [zhemao] has done. He created EZ8, an 8 bit processor is written in Verilog. EZ8 has a 3 stage pipeline, which makes design very interesting. Instruction set pipelines have been used in processors for many years. They speed up operation by allowing the processor to execute more than one instruction in parallel. The idea is similar to washing, drying and folding laundry. Most people pipeline their laundry. One load is in the washer, another in the dryer, and a third is being folded. Pipelines aren’t a free lunch though – there are hazards. If one instruction requires the result of an instruction which is still being executed in parallel, there’s a problem. In our laundry analogy this would be like having one sock on the folding table while its mate is still in the dryer. The folding operation must wait for the drying operation to complete before the socks can be paired. This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.
[zhemao] didn’t just give us a processor and no support though. He also included an assembler written in OCaml, and an emulator written in C. Several test assembly programs are also up on [zhemao’s] github repo to verify operation. [zhemao] has tested his processor with Altera Cyclone 5 series FPGAs, but it should be possible to port it to other FPGA manufacturers. If you want more information, [zhemao] also has a discussion going on in the ECE subreddit.
[Thanks for the tip LongHornEngineer!]
[Image courtesy of intel]
17 thoughts on “Design Your Own Processor With Verilog”
Can it run MS-DOS?
> This is exactly how assemblers handle the situation – they insert NOPs between known hazard instructions.
Not anymore. MIPS (and perhaps other ancient RISCs) used to expose hazards in the machine code directly–in the form of a branch delay slot, for example–but newer designs such as ARMs and even more recent MIPSs have since stopped using this technique.
As I understand it, exposing hazards in ISA makes no sense for advanced designs, such as those featuring superscalar or speculative execution.
A big disadvantage of exposing hazards in the ISA is that you can’t improve the design at a later time, without making the ISA incompatible.
Well, you can emulate the hazard (which I think is exactly what never MIPSes do). But it’s kind of defeats the purpose of putting them there in the first place.
I remember I think Itanium leaving OOO hazards handling to the compiler?
Yes. That didn’t serve Itanic very well ;)
Sparc has delay slots… I guess it has ancient origins but they are also some of they fastest database processors made nowadays… if you have the money to by them. I have a T2000 and other asorted older Sparc machines… quite alot of fun :D
Wikipedia indicates that most RISC architectures have 1-2 delay slots the exceptions are Power Architectures, ARM and Alpha…
It would be interesting to implement branch predicting and shortcutting.
Can this be used to design a specialized giga-hash processor for SHA-256 or Scrypt for cryptocoin mining? There have been ASIC systems announced for Scrypt but the prices are just insanely high.
The answer is always pretty much going to be no. The cost in producing these chips is mammoth, making the masks and doing a production run is into the millions of dollars. Once you’ve sunk those costs you have tens or hundreds of thousands of packaged dies at your disposal.
Do you mine with them, sell them at cost, or sell them at a massive profit? Pretty much everybody is going to go for number three, with three you don’t have to deal with megawatt sized data centers and cooling the things. Bitfury did both, he made millions selling his packaged chips and then used the money to make his own datacenter. At this point he owns most of the hashing network and probably hundreds of tens of dollars at this point.
Would you sell them at cost? Nobody else is, that’s why the price of the is so high.
You don’t need a CPU for SHA-256. All you need is the hashing function, a match for results, and a communication interface. But it’s too late for FPGA SHA-256 mining, anyway.
Interesting post,will have to look at the code,as i am trying something similar.
About hazards and the above comments, Tomasulo ftw…
Good work zhemao, thats very cool
That’s a really cool project, and I know it took a lot of work….
ez8 is already taken. By the z8 encore chip. It’s like the ez80 for the z80, but for the z8 line of microcontrollers.
The funny thing is, I’m pretty sure this is a better CPU.
When I saw this I thought it was a zilog ez8 in and FPGA.
Better is all realitive. If it does the job and is cheap that is all you need.
I spent the day designing a simple CPU in verilog, then I decided to take a break and read hackaday.
My home-made S16X4A MISC architecture CPU is up on Github. http://github.com/sam-falvo/kestrel . Click on cores/ then S16X4A. Docs included.
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