CMOS opened the door for many if not most of the properties needed for today’s highly integrated circuits and low power portable and mobile devices. This really couldn’t happen until the speeds and current drive capabilities of CMOS caught up to the other technologies, but catch up they did.
Nowadays CMOS Small Scale Integration (SSI) logic families, I.E. the gates used in external logic, offer very fast speeds and high current drive capability as well as supporting the low voltages found in modern designs. Likewise the Very Large Scale Integration (VLSI) designs, or Very Very Large Scale if you like counting the letter V when talking, are possible due to low power dissipation as well as other factors.
How CMOS is Designed
CMOS, which means Complementary Metal Oxide Semiconductor, is based on combining two polarities of MOSFETS; Metal Oxide Semiconductor Field Effect Transistors.
Regular transistors, known as Bipolar Junction Transistors (BJT) meaning that they are made from junctions that have a positive and a negative (PN) junction utilize current as the input and create gain by controlling output current. As all of these current flows add up it means that at the end of the day there is a lot of current flowing which results in power being dissipated which ultimately results in heat.
The Junction Field Effect Transistor (JFET) utilizes voltage instead of current on its Gate input, somewhat like the Base on a Bipolar Transistor, to control the output voltage. Since the Gate is not insulated from the other terminals, known as the Source and Drain, there is a leakage current in JFETs that would not be present if the Gate was insulated from the Source and Drain.
Enter the Insulated Gate FET (IGFET) which is the basis for most of the transistor devices found on large scale integrated chips today. Looking at the diagram, the MOSFETs all show a distinct space between the Gate and the rest of the structure. The other two pins are the Source and the Drain.
This is a real gap created by silicon dioxide, the “Oxide” in MOSFET. If that sounds like glass, a really good insulator, I would say well yes it is. If a good insulator sounds like a dielectric, the makings of a capacitor, I would also say that well yes, it is. FET’s come in two major modes of which there are two different types based on polarity. The major modes are Enhancement and Depletion.
An enhancement MOSFET needs a voltage applied to a gate for the device to turn on, it can be thought of as a normally closed switch as opposed to a depletion mode device which needs a gate voltage applied to turn off and can be thought of as a normally open switch.
FET’s come in two different polarities based in part upon the polarity of the Gate signal and how it affects the device: An N-Channel device is activated when a positive voltage is applied to the Gate compared to the Source and a P-Channel activates with a negative voltage.
By combining an N-Channel device and a P-Channel MOSFETs an inverter is implemented. When the Gate is High the N-Channel MOSFET turns on pulling the output Low. Likewise when the Gate is Low, the P-Channel MOSFET is turned on pulling the output High. Note the alternate way to draw the MOSFETs on the right that is a tad more intuitive as the bubble on the P-Channel indicates that a Low on its Gate will turn it on.
Unprotected CMOS Can Be Fragile
The High Impedance on the input, I.E. the lack of a load resistance to a ground, means that a little bit of static charge on something like the human finger, can actually be disastrous for an unprotected CMOS circuit. A simple spark or otherwise invisible charge can ruin a MOS based device by punching holes in the gate insulation. Another problem caused by excessive voltage is what is called “SCR Latchup”, basically an excessive voltage causes the PNPN junctions produced by layout to act as back to back transistors that cascade into full conduction resulting in a short circuit between power rails. The only way to relieve the shorted condition is to remove power from the device which allows all of the energized transistors to turn off. The addition of protection diodes as shown is pretty standard across the board, though sometimes the diode function is really implemented with on board JFETs.
Let’s talk about CMOS logic families. The table below shows the curve between the newest families and obsolescence. Many of the comments on the video on TTL properties mentioned that TTL is for the most part “mature”, old, and/or obsolete. While this may be true in general, the legacy of TTL logic levels lives on in the form of TTL compatible families, usually denoted by a “T” in the family name.
CMOS vs. TTL
The voltage levels of CMOS based logic are somewhat different from TTL, basically instead of the preset levels of Low(.4-.8v) and Hi(2-2.4v) the input logic levels of CMOS are mostly expressed as a ratio of the supple voltage.
The output voltages are usually within a few tenths of volts of each rail and the input thresholds are generally 1/3 and 2/3 of the supply voltage for Low and High respectively. This has the effect of maximizing the noise margin as the near rail-to-rail output swing (from near ground to near the power supply) ensures that the gate has the maximum output voltage swing.
It’s important to note the CMOS works best and uses the least power when the gates are turned all of the way on or all of the way off, it is very important that the voltage be kept out of the area shown in pink on the table.
CMOS outputs can generally connect to TTL inputs providing that the CMOS output can supply enough current. Feeding a CMOS input from a TTL output is a bit more problematic as the TTL output of 2.4V in a 5 volt system is not high enough to guarantee a High is seen by the CMOS part. Generally a pullup resistor can supply the last little bit of voltage but a cleaner approach is to use a “T” type CMOS part such as an HCT instead of HC, or a AHCT instead of AHC.
Low Voltage and High Speed
The chart below shows the migration CMOS has made over the years as it increased speed and ultimately support for the lower voltages; down to 0.8V as shown. The technology trend ends up with older families in the upper right, the newer and more advanced families down in the lower left. During this time other attributes also improved including output current with 24-60ma drive current becoming not uncommon. Low voltage and higher speed do tend to go hand in hand as the voltage has less “distance” to slew. With the new voltages come some other issues such as translating between them which I will cover just a bit in the next post.
In the next video I will show some CMOS logic family capabilities that include supply voltage translation such a 3.3v to 5v and also including down to 0.8v, a bus “hold” function, and will try my hand at showing how to lay out a CMOS gate and what some of the various layers and technologies are that are used in CMOS fabrication.
For your quiz this week, what logic function does the following drawing depict :