If you want a stable oscillator, you usually think of using a crystal. The piezoelectric qualities of quartz means that it can be cut in a particular way that it will oscillate at a very precise frequency. If you present a constant load and keep the temperature stable, a crystal oscillator will maintain its frequency better than most other options.
There are downsides to crystals, though. As you might expect, because crystals are so stable it’s hard to change the frequency much when you want a different one. You can use a trimming capacitor to pull the frequency a little, but to really change frequency, you have to change crystals.
There are other kinds of oscillators that are more frequency agile. However, they aren’t usually as stable. To combine flexibility with crystal-like stability, you can use a Phase Locked Loop (PLL). Many modern systems use direct digital synthesis, but the PLL is a venerable and time-tested technique.
The basic idea is simple. A PLL uses a crystal oscillator, but it isn’t the main output. The primary output is from an adjustable oscillator, usually a voltage-controlled oscillator (VCO). Consider a simple (but impractical) example. Suppose the VCO should put out the same frequency as the crystal oscillator. The loop part of PLL is where you compare the two frequency outputs and develop a voltage proportional to the difference. This voltage adjusts the VCO until the output matches.
This raises two questions: First, why not just use the output of the crystal oscillator? Second, how do you compare the output of the oscillators?
Let’s answer the second question first. Consider the case where both oscillators output square waves. You could consider the low level a logic zero and the high level a logic one. Feeding both outputs into an XOR case will result in an interesting output.
If the two signals are exactly in phase, then the inputs will be either 00 or 11. In both instances, the XOR gate will output a zero. The only way the inputs can always be in phase is if they are exactly the same frequency (and in phase, of course). Any frequency or phase error will generate high outputs. Even better, the output of the XOR gate will have a duty cycle proportional to the amount of error.
Consider the extreme cases. One extreme is where the crystal and VCO output matches exactly. The output of the XOR gate will be a steady low. The other extreme would be where the VCO output is stuck low (0 Hz). Then the output of the XOR gate will be the same as the crystal oscillator’s output. Other cases will cause outputs of pulses and the closer the two frequencies are, the less total time the output will be high.
This is probably easier to visualize than read about. The Falstad simulator can show you a phase detecting XOR gate in your browser. Try changing the frequency from 105 Hz to other frequencies and observe the output. If you alter the frequencies to match while the simulation is running, you will probably still have a phase error. Try the Reset button to see what happens when the frequency and phase match.
The Low Road
Given a train of pulses, you can use an RC circuit to integrate the pulses (that is, develop a voltage proportional to the area under the pulses). This is a suitable voltage to feedback to the VCO. Depending on the VCO, you might need to process the voltage a bit, but that depends on exactly what circuit you are using.
There are other ways to do phase detection. For example, here’s another way to do it (see right). There’s probably plenty of other methods, too. The key idea is to compare the two frequencies and generate an output that can influence the VCO. When the phase (and, thus, the frequency) match, the output voltage will be stable at the level required to match the frequency.
So far our PLL is a little underwhelming. It is hard to imagine why you wouldn’t just use the crystal oscillator. The magic happens when you change the output frequency in some way. For the most part, that means dividing the output frequency before the phase comparator. If you do that, the loop will lock the divided frequency to be the same as the crystal. That will produce a higher frequency at the output.
For example, above is a PLL that generates a frequency four times the reference oscillator. The two flip flops divide the output frequency by four, so the phase comparator locks the output frequency to 4X the reference frequency. Try changing the reference clock to, say, 10 Hz. Then try 100 Hz or 500 Hz. You’ll notice when you modify the clock it takes a bit for the loop to lock. For example, below is the output switching from a 10 Hz to 100 Hz reference (40 Hz to 400 Hz output).
You can see the output jitters a bit before it settles down. Of course, dividing by four is just an example, you could divide by any number (often called a divide by N circuit) to produce different frequencies.
This scheme has a few advantages. First, the crystal oscillator can be a low frequency which is easier to build and make stable. If you have a programmable divider, you can generate many different output frequencies. However, you can’t just create any frequency you want. For example, suppose your reference frequency was 100 kHz. If you divide the output by 10, the output will be 1 MHz. If you divide by 9, you’ll get 900 kHz. Good luck trying to create 925 kHz.
One common solution to increase the frequencies you can create is to also divide the reference clock. This is often called a divide by N/M scheme. In the above example, suppose you could divide the reference clock by 1, 2, or 4. Now setting N to 10 you could produce 1 MHz, 500 kHz, or 250 kHz. Divide by 9 would result in 900 kHz, 450 kHz, and 225 kHz. You still can’t produce any arbitrary frequency, but you can get more frequencies. The 925 kHz you couldn’t do before? Just use M=4 and N=37. The reference frequency, then, is 25 kHz and 925/37 is 25. You can also think of it as dividing the output frequency by N/M to get the original reference frequency (925/(37/4))=100).
So far, you’ve seen a PLL essentially multiplying a reference clock by some integer factor. However, it can do more than just that. For example, PLLs can demodulate FM and AM (hint: the phase detector’s voltage output tells you how far off an FM signal is from the center). PLLs can also recover clocks from data, deskew clocks transmitted over long lines, and, using a lock-in amplifier, a PLL-like circuit can recover data from very noisy signals.
There’s plenty of details I’ve glossed over, and there are whole books written on the topic. However, if you want to explore more, [Jeri Ellsworth] and our own [Bil Herd] created a video on the subject you’ll enjoy (see below). There are many implementation options. You can create a PLL in software, even. If you want a one-chip solution, the CMOS 4046 IC comes to mind.