We’ve been fans of the Yosys / Nextpnr open-source FPGA toolchain for a long while now, and like [Michael] we had no idea that their oss-cad-suite installer sets up everything so that you can write in Verilog or VHDL, your choice. Very cool!
Verilog and VHDL are kind of like the C and ADA of the FPGA world. Verilog will seem familiar to you if you’re used to writing code for computers. For instance, it will turn integer variables into wires that carry the binary values for you. VHDL code looks odd from a software programmer’s perspective because it’s closer to the hardware and strongly typed: an 8-bit integer isn’t the same as eight wires in VHDL. VHDL is a bigger jump if you have software in your brain, but it’s also a lot closer to describing how the hardware actually works.
We learned Verilog, because it’s what Yosys supported. But thanks to GHDL, a VHDL analyzer and synthesizer, and the yosys-ghdl-plugin, you can write your logic in VHDL too. Does this put an end to the FPGA-language holy wars? Thanks, Yosys.
[Michael] points out that this isn’t really news, because the oss-cad-suite install has been doing this for a while now, but like him, it was news to us, and we thought we’d share it with you all.
Want to get started with FPGAs and the open-source toolchain? Our own [Al Williams] wrote up a nice FPGA Boot Camp series that’ll take you from bits to blinking in no time.
Digikey’s introduction to FPGA is what I used to get started, though I’m sure Al’s boot camp is great, and the video nature of Digikey’s stuff did make referencing it difficult at times (and IIRC he used logic as an impromptu clock signal at one point, a big no-no which he acknowledged in a later vid).
I wrote just enough Verilog to be able to really understand it (PWM, UART, an ultrasonic transceiver module, PID, an SoC based around picorv32). Importing and wiring up modules gets to be a real drag, especially if you have multiple instantiations, and especially if you want to instantiate instances of a module in multiple locations of a design. I’m not a purist that objects to its c-like syntax on principle, but I find it clunky in general, and there’s been a lot of tooling development that’s happened since that could catch a ton of bugs pre-synthesis (the one most easily at-hand is state machine enum completeness checking, and defining enums alongside their binary value is redundant and error-prone in and of itself).
I haven’t touched VHDL, and a lot of people like it better, but there isn’t much going on with it in the open-source design world. Yes, yosys understands it, but if one is going to learn one of the industry standard HDLs, it seems to me that Verilog is the way to go. I also read enough complaints about it that it seems like it would merely be taking time to switch to the lesser of two evils.
I’ve been moving into SpinalHDL, and it’s a breath of fresh air. It’s just my hobby stuff, so integration into larger Verilog/VHDL codebases isn’t a consideration for me, just my own time and sanity. It can output Verilog or VHDL, so you can just plug its output into your typical sim/pnr workflow.
There’s also something about VHDL / Verilog being differentially accepted in industry in the US / EU, but that’s just hearsay on my part.
An important caveat on using VHDL with oss-cad-suite is that it doesn’t get bundled with the Windows builds (understandable, but disappointing). On Linux and Mac it works perfectly, but it makes VHDL just a little bit harder to use in workshop contexts.
Good to know! B/c honestly workshops are where such a simple-to-install toolchain shines.
Hmm. Knew about the VHDL support, didn’t know about the installer.