The phase locked loop, or PLL, is a real workhorse of circuit design. It is a classic feedback loop where the phase of an oscillator is locked to the phase of a reference signal using an error signal in the same basic way that perhaps a controller would hold a temperature or flow rate in a physical system. That is, a big error will induce a big change and little errors induce little changes until the output is just right. [The Offset Volt] has a few videos on PLLs that will help you understand their basic operation, how they can multiply frequencies (paradoxically, by dividing), and even demodulate FM radio signals. You can see the videos below.
The clever part of a PLL can be found in how it looks at the phase of two signals. For signals to be totally in phase, they must be at the same frequency and also must ebb and peak at the same point. It should be clear that if the frequency isn’t the same the ebbs and peaks can’t line up for any length of time. By detecting how much the signals don’t line up, an error voltage can be generated. That error voltage is used to adjust the output oscillator so that it matches the reference oscillator.
Of course, it wouldn’t be very interesting if the output frequency had to be the same as the reference frequency. The clever trick comes by dividing the output frequency. For example, a 100 MHz crystal oscillator is difficult to design. But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.