There is a wide assortment of cheap development (dev) boards for Complex Programmable Logic Devices (CPLD), the smaller cousin of the Field Programmable Logic Array (FPLA)
Using an inexpensive board and the development software that’s free to download from the major programmable companies such as Xilinx and Altera, the only additional thing needed is a programmer module. Cheap ones are available on Ebay but I am hoping that someone takes the time to teach an ARM/Arduino to step in as a programmer.
I have a small collection of dev boards including some Ebay specials and also designs I did a few years ago to choose from. For today I am grabbing a newer board that has not been fully checked out yet; an Altera Max V device. I have stuffed the CPLD, the clock oscillator, some LED’s and part of the onboard power supply along with the JTAG header needed to program the CPLD and that’s about it.
On the outside the important signals are a master clock (NOTHING happens without a clock) and then there are the LED outputs that let us know something is going on. In the old TTL days you usually couldn’t drive an LED directly, so that ability in itself is a sign of the times.
Starting with the clock input you can see the pin and oscillator below. We will use settable parameters in the software to wire this input to the low-skew global clock (gclk) distribution network. The difference between when the clock arrives at the various register across the entire device is known as skew and if it is noticeably late or early to some blocks it could have a drastic effect on the logic. (latches old or intermediate data when everything else latches the current data.
The 22 Ohm resistor in the clock flow is placed near the oscillator and matched impedance and absorbs reflections, but more on that in a different video.
Once the clock makes it into the device we need to get it connected to the global clock. This is accomplished at a schematic level, and I chose to use a schematic on the top level, by adding a primitive marked Global. If using an HDL language you would specify a global primitive as well.
Once connected to the global clock, there are also auxiliary clocks and “regional” clocks for different zones, which look like this:
The drawing above is an over simplification, one of the Altera Max logic blocks actually looks like the diagram below.
A very important concept while living on a chip is that it is unsafe to try to predict a minimum delay and that gates in nearby silicon are so fast the simple logic may propagate glitches or unknowns. All of these issues affect the suitability of using combination logic to drive a clock input. A good technique is to do a fair amount of computational calculation and then stop to save the results in a register with a global clock, a technique referred to as pipe-lining
An example of reverting back to clock driven may look something like this for detecting a rising edge.
At some point we need to interface to the outside world. In a heavy utilization design the PCB layout waits until the programmable logic is significantly done, at least enough that it would still be compileable even with the pin assignments permanently frozen (the compiler loves to pick its own pins). In my case I froze the pins already when I designed the PCB and assignments can be seen here.
I named the pins to reflect the pin number that matches the PCB and so I can easily connect up the pins from the inside.
As I mentioned I like to have a schematic as the top sheet of the design and I do any sizing or inversions there as it is more intuitive for a dinosaur like me. Our design will look like this when completed with a 64 bit counter dividing down the 50Mhz clock to something visible.
We have yet to define the counter, which I call ncounter as I will make it n bits large depending on a parameter I set. Using an editor and the nine fingers left to me I created this overly simple file. I say overly simple as I didn’t include reset and other housekeeping logic that helps both the physical and the simulation results (I say nine fingers because I tore one-off last summer).
Once typed and saved a click causes the “Create Symbol” command is run and the ncounter symbol is created. The parameter that sets the width defaults to 7 (8 bits) but is overridden with 64 bits pushed down from the top sheet.
Finally I show a little of how I dealt with the fact that the Max V device has a core voltage of 1.8v and I have elected to run the interface pins at 3.3V making this a dual voltage part. I use Proteus by Labcenter for schematic and PCB ($248USD) and one of its strengths is that it has a powerful auto-router that routes faster and better than I ever could. I don’t hand route as inevitably there will be changes and the time spent re-hand-routing is time I don’t have. So essentially I teach (constrain) the auto router how to do better each successive pass.
This is a 4 layer board with ground as the 2nd layer (from top) and +3.3V as the third layer since it was used by the peripheral chips as well. That left the need for routing the core 1.8V supply for the CPLD.
As shown below I created a loop shaped supply path for the 1.8V supply with a couple of internal interconnects on the two inside layers. I jump layers often so that ground return (and +3.3) current can follow straight paths to the sources and not have to go around to find an exit path. Also the center maintains a lower impedance rather than being isolated by being surrounded on almost 4 sides.Having a loop reduces both DC and AC resistance as not only is there parallel paths at work, there is no stub for things to reflect off of. Stubs are typically bad.
Using the programmer built into the software I upload the code after I compile it and the LEDs blink. You don’t have to take my word, you can watch the video… I promise there is very little CGI at work.
While this is just the briefest of run-throughs, if you followed along you have experienced all of the steps to program a CPLD or even an FPGA.
I am thinking about taking the version of this PCB that not only has the fast SRAM but also voltage level converters to allow the interface to voltages like 5v. One thought is to make an Arduino driven logic analyzer since the Arduino doesn’t need to run “at speed” – the CPLD hardware takes care of all of that.