The ESP: A New 1kB Contender Appears

The ESP8266 is officially checking into the Hackaday 1kB Challenge. Doing something meaningful in 1kB of compiled code is tricky; modern SDKs like the ones often used for ESP8266 compile even the simplest programs to nearly that size. If you want to use this hardware in your 1kB Challenge entry, I have a solution for you!

The ESP8266 now has a barebones build environment focused on minimizing code size, as little as 131 bytes to boot up and blink an LED. It also “supports” some new, insane clock rates (like 346 MHz) and crazy development cycle speeds. The WiFi is stuck in “airplane mode,” but it will be worth your time to consider the ESP for the next non-WiFi project you’ll be doing.

Far too often, we follow design patterns that ‘just work’ instead of looking for the ones that are optimal because we’re afraid of wasting time. The benefits of keeping code tight and small are frequently overlooked. When code is small and environments minimal, RAM and FLASH become easier to come by, compiled binaries shrink and time wasted by compiling and flashing can decrease by an order of magnitude! We rarely see just how much value is added when we become a good engineer: being done only when there’s nothing left to remove from a design. Nosdk8266 will let you see what it’s like to test out code changes several times a minute.

Just a month ago, when preparing the ESP8266 for a USB bootloader, I had to make a stripped-down environment for it. It’s not based on the Official Non-OS SDK or the RTOS sdk, but an environment that can boot up and blink an LED. Not just blink an LED, but tweak the clock in some totally unexpected ways and even run the I2S bus (used for espthernet and Color NTSC Broadcast Video). If you’re not at the submission phase for your 1kB challenge, you can even use the mask ROM for printf! Now you can tweak your code and — in under 2 seconds — see what the new code does!

Even in PICO mode, the part still has to use the mask ROM to be loaded, but thankfully, the 1kB Challenge has added an exception for unavoidable bootloaders. No longer bound by the shackles of WiFi, I can’t wait to see what you’ll do with the ESP8266. Just beware that the processor may not work reliably when overclocked at 346 MHz (332.5%,) and you’ll certainly be voiding any warranties you may have. Sounds like fun, right?

Editorial Note: This is a guest article from Charles Lohr, aka [CNLohr]. Although he has written a few other guest articles, he is not a regular contributor to Hackaday and therefore, this article does not disqualify him from entering the 1kB Challenge. We felt it more fair to publish this article which shares the tools he’s using to make code smaller, rather than to keep them to himself for fear of disqualification. While we have your attention, we wanted to mention one of Charles’ articles which was published on April 1st — we still think there’s a lot of people who don’t realize it wasn’t a prank.

27 thoughts on “The ESP: A New 1kB Contender Appears

  1. This is excellent. I have been trying to point out to people that they should think of the ESP8266 beyond being an “add on device to get Wifi”. It is a dandy little controller (and dirt cheap too). It is easy enough to turn off Wifi using the standard SDK as well. Anyhow, nice work and glad to see someone else nudging people towards using ESP8266 devices for things other than wifi.

        1. indeed. If they could close timing across process corners @320Mhz then you would see that as a max in the datasheet. Since they don’t show that then at the specific instance of cnlohr’s board @his VDD + temp you get 320. That said, a good job was done by Espressif to have the Xtensa and its subsystems work at 320. This is also at 40nm btw. If they moved process nodes this would improve further. It would be interesting to know which net is the slow one on the part that produces the datasheet #s. These chips typically are designed using tool called prime time (or equivalent) that produces a report that the SoC leads study very carefully. After the part comes back, a matrix lot is then used to determine the max across process corners. Then, conservatively (+/- VDD%. -40 +80) as you see, the part is spec’d.

  2. Thanks Charles, for sharing this tiny but great environment and more in-depth knowledge of your “precious” :)

    With wifi disabled and those cpu and bus overclock settings, can you still use DMA with I2S reliably ? And how does it practically affects GPIO interrupts latency now ? (in regards to the 17 cycles lag at 160Mhz that hitted your USB implementation at high speed… any good news on this front ?)

    1. Every test I’ve run (at the 346 MHz speed, not the 389 MHz speed) shows I2S and GPIO act exactly as they would at the 80/160 MHz speeds. Same 17 cycle delay – but in wall clock time it is much lower. I2S operates at 173 MHz, not 80 MHz like butter.

      1. This is really amazing, I can’t believe it can run at 389mhz. The more i learn about this little chip the more I wonder how they could afford to sell it so cheaply. People like yourself putting in the ground work need more recognition. I applaud you.

        1. I get far more credit than I should have. People like IGRR, Angus, PFalcon, jcmvbkbc *** Big one for this dude. As well as the other organizers like Robert and I’m sure far more I don’t know! They’re all hidden in the background with far more work than I’ve put in.

        2. >the more I wonder how they could afford to sell it so cheaply

          its the other way around. ST, TI NXP Atmel etc (or whoever the F owns them these days) simply rip into your asshole when you buy their parts. The real cost of silicon at those sizes does NOT factor into the price of a part – packaging is a more significant cost than wafer, the biggest cost driver is supporting tens of thousands employees at those corporations, and CEO bonuses.
          16-160MHz, 4-64KB onboard sram, flash size – its all artificial market segmentation designed to extract maximum revenue from all potential customers.

          ST is a good example, they dont even bother to disable parts of the chip when binning, their low end stm32f103 (T6, C8T6) parts ship with unlocked 128KB of flash, Size limit triggers on the chip ID in the programming software.
          Then you have stm32f103 semi clone Giga Devices GD32F103CBT6 which is an 128KB SRAM array with a huge flash chip glued to its ass, easily 5-8x the silicon, faster and at a lower price.

          1. There is a lot of development for SW, compiler, libraries, bug fixing, app notes and use cases, documentation, dev boards. There are licence fees for IP cores and dev software, seminars, verified supply chains, product variety and still some employees in western countries; maybe even yours; maybe even your neighbour. Still, there are/were free parts for you, discounts for schools, and so on.
            In general, some of the smaller ICs could have a flaw/failure in one of their deactivated areas and/or the deactivated areas could reduce licence fees for this particular IC.
            I like the change that Espressif brought but please lets keep things in perspective.

          2. “Discounts for schools” = Selling the parts at only a significant profit instead of an insane profit.

            The ESP has totally replaced any project it can be used in EXCEPT the places where I use AVRs in commercial applications. AVRs are just such tanks, I can put it in a design and trust that it will keep ticking for 20 years in all (rather expensive) 1,000 units I just got made.

            I hope the Chinese PCB market gets US PCB producers’ attitude fixed. The same as I hope Chinese chip producers fix worldwide semiconductor companies attitudes. Everyone’s stuff is a commodity, they better start to act like it.

          3. “its all artificial market segmentation designed to extract maximum revenue from all potential customers”

            BS. “Artificial” market segmentation has been part of the digital semiconductor industry (among others) for most of its existence. It allows companies to spread R&D expenses, manufacturing resources, inventory risk across a large volume. It helps them realize economies of scale that would not be possible otherwise.

            The alternative would very likely be more expensive, less capable chips at every level. And no, Clones aren’t a counterargument — They depend on skimming off the volumes (and price points) established by the devices they clone.

            It’s great that the ESP chip line is currently simple and inexpensive, perhaps it will stay that way, or perhaps they will follow a similar path to other semiconductor startups.

          4. cnlohr (Charles):
            There are many reasons that make an IC pricey, some of which [eas] and myself pointed out.
            You like cheap uCs with great features – me too. Should western companies have done things better and should they do things better: Yes.
            However, you and [rasz_pl] make it sound as if western companies knew how to do something like ESP8266 but just didn’t want to. They really couldn’t. Some of the things that Espressif did, could ruin western companies. Also, environmental standards, industrial standards, safety standards,…, taxes, law and wages are different. And I still don’t know for sure who is paying the shipping for my orders from China – certainly not me in person and not the Chinese company. All this brings me back to my initial statement:
            I like the change that Espressif brought but please lets keep things in perspective.

          5. But western companies did know how to do something like ESP8266, and they did. Famous TI CC3x00 at what was it? $30 per chip? $40 when introduced? Its still >$20 NOW ….

          6. I have already explained some of the reasons and so did [eas] and there are even more.
            Times change rapidly. I hope that this movement becomes more than only shifting from western to Chinese companies.

    1. I felt really nervous after submitting this article for review – and especially when I started seeing some homebrew CPU projects show up as submissions. I kinda feel like using the ESP for a 1kB project misses the intent-of-the-contest’s mark.

      Also, I still feel funny about the position people see me in with all of this. I am just a midget sitting on the shoulders of giants. For instance, I was helpless to set up the PLL at all if it weren’t for pvvx’s herculean reverse engineering work with the SDK and mask ROM. All I did was spend a couple hours playing with constants till I saw a pattern.

      1. I think one of the marks of a great person is their eagerness to share the credit out. You should feel justifiably proud that you have helped communicate the great work that you and others have done. Your attitude of never taking limits as given but instead investigating the boundaries for yourself and as a result redefining them is at the core of the true hacker mentality. I salute you and your fellow giants!

  3. This is cool and a excellent development hack for sure. But is is kinda funny to hear the excitement for blinking a led in “only” 307 (or whatever the actuall number was – I forgot) bytes. Back in the day when I started playing with computers back in 1977 here was a chess program for the 6502 KIM-1 that was good enough to beat the 12-year old me most of the times. The machine had 1 k ram and the stack and the monitor ROM used part of that ram as well…

    40 years of development have taken us from 1MHz 8-bit to 3xxMHz 32-bit. For the hardware. But the roughly the same amount of code took us from chess to a led blinker. ;-)

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