You probably couldn’t write a decent novel if you’d never read a novel. Learning to do something often involves studying what other people did before you. One problem with trying to learn new technology is finding something simple enough to start your studies.
[InfiniteNOP] wanted to get his feet wet writing CPUs and developed a simple 8-bit architecture that would be a good start for a classroom or self-study. It is a work in progress, so there may be a few bugs in it still to squash, but squashing bugs might be educational too. You can read the documentation in the HACKING file for details on the architecture. Briefly, the instruction’s top four bits encode the operation, while the last four bits select the register operands (there are four registers).
[InfiniteNOP] used the Xilinx tools to simulate and synthesize the CPU, but we thought it might be a good excuse to play with EDAPlayground. You can find a testbench that works with EDAPlayground, although you’ll probably want to update the CPU files to match the latest version.
You won’t want to use a simple processor like this in a real project, but as a learning tool, it is about the right size to be manageable. You can graduate later to more complex designs. If you need a brush up on Verilog, have a look at the video below.
4 thoughts on “Teach Yourself Verilog With This Tiny CPU Design”
“Nand to Tetris” (http://www.nand2tetris.org/) is also worth a look, along very similar lines.
A friend and I made a Verilog CPU for a class project. We decided to use a microcode implementation to execute instructions, given the type of architecture it was asked of us [a single accumulator architecture with a common datapath]. Extending the CPU instruction set was just a matter of adding an entry in the decoder ROM and adding the corresponding microcode on the microcode ROM. We tested the CPU on an FPGA as well, mapping the 7-segment display to the instruction register and the switches and LEDs to memory address 0xff.
For bootstrapping yourself in Verilog, a CPU would not be my recommendation, especially if you want code that synthesizes properly into an FPGA architecture or that you can port to other tools such as Cadence’s Virtuoso to tape out in silicon.
hehe, when I decided to learn verilog, I had already decided that I wanted to design a CPU, and I read a textbook on digital logic before attempting this, so I believe this helped me immensely. As mentioned in the article, I have tested its synthesizability by using Xilinx ISE (even though I am going to get rid of that for loop ;-P)
Anyway, this Virtuoso thing seems interesting. Does it accept HDL input? (Of course, manufacturing an IC is out of reach for me, but I did not know you could do it by writing in a HDL. If there is a free version, I might try feeding the design to it and see how it synthesizes to silicon.)
You are correct on stating that reading a textbook on digital logic is of great help before embarking on this task. I do not claim to be an expert in HDL or anything like that, and it is not my intention to put you down in your efforts. I believe it is great that you are going in to deep waters without fears.
If you mean the for loop you have in your register file module, that one gets flattened at synthesis time. A cursory look at your HDL reveals no extraneous logic or things that could potentially backfire on you.
Regarding Virtuoso, yes, modern digital design uses HDL, which gets simulated against technology files using software like Synopsys Design Compiler in order to do power analysis, clock analysis, capacitance analysis and all that good stuff. The HDL eventually gets carried over to other tools, like Virtuoso, which allows you to lay out the silicon. This process is usually known as Design Verification and Full Custom VLSI. The idea is that you do not want to have to manually convert your high level primitives into discrete transistors, but have some tools to aid you in the process. Fabrication houses will provide you with technology files that you can use with VLSI tools, as to help you with the process. It’s actually a fun, lengthy task which is done by a large team.
Please be kind and respectful to help make the comments section excellent. (Comment Policy)