Relay Computer: You Can Hear It Think

Modern digital computers have complex instruction sets that runs on state-of-the-art ALUs which in turn are a consequence of miniaturized logic gates that are built with tiny transistors. These tiny transistors are essentially switches. You could imagine replacing with electromagnetic relays, and get what is called a relay computer. If you can imagine it, someone’s done it. In this case, [jhallenworld].

The Z3 was the first working programmable, fully automatic digital computer designed by Konrad Zuse. The board employs modern semiconductor devices such as memory and microcontrollers, however, the CPU is all relays. A hexadecimal keyboard allows for program entry and a segment display allows tracking the address and data. The program is piped into serial to the parallel decoder and fed to the CPU where the magic happens. Since the core is electromechanical it is possible to connect the output to peripherals such as a bell as demonstrated near the end of the video.

This project is a good balance of retro and modern to be useful to anyone interested in mechanical computers and should be a lot of fun for the geek kind. Hacking this computer to modify the instruction set should be equally rewarding and a good exercise for students of computing theory.

There is a SourceForge page dedicated to the project with the details on the project including the instruction set and architecture. Check out the video below and if you are inspired by the project, be sure to check out the [Clickity Clack]’a Videos on designing a relay computer bit by bit.

You Know You Can Do That with a 555

Hardly a week goes by that we don’t post a project where at least one commenter will lament that the hacker could have just used a 555. [Peter Monta] clearly gets that point of view. For a 555 design contest, he created both digital logic gates and an op amp, all using 555 chips. We can’t quite imagine the post apocalyptic world where the only surviving electronic components are 555 chips, but if that day were to come, [Peter] is your guy.

Using the internal structure of the 555, [Peter] formed a basic logic gate, an inverter, latches, and more. He also composed things like counters and seven-segment decoders. He had a very simple 4-bit CPU design in Verilog that he was going to attempt until he realized it would map into almost 400 chips (half of that if you’d use a dual 555, but still). If you built this successfully, we would probably post it, by the way.  You can see a video of the digital logic counter, below.

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Find Instructions Hidden In Your CPU


There was a time when owning a computer meant you probably knew most or all of the instructions it could execute. Your modern PC, though, has a lot of instructions, many of them meant for specialized operating system, encryption, or digital signal processing features.

There are known undocumented instructions in a lot of x86-class CPUs, too. What’s more, these days your x86 CPU might really be a virtual machine running on a different processor, or your CPU could have a defect or a bug. Maybe you want to run sandsifter–a program that searches for erroneous or undocumented instructions. Who knows what is lurking in your CPU?

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Virtual CPU Stays on Script

Some will see it as a great thing, and others as an example of how JavaScript is being abused daily, but [Francis Stokes] decided to design his own CPU architecture and implemented a virtual version of it using JavaScript. The CPU is a 16-bit affair and has a simplified assembly language. The code is on GitHub, but the real value is [Francis’] exposition of the design in the original post.

While discussing the design, [Francis] reveals his first pass at the instruction set, discussed what he found wrong about it, and then reveals the final set composed of real instructions and some macros to handle other common cases.

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VexRiscv: A Modular RISC-V Implementation for FPGA

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

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Simulating the Learn-by-Fixing CPU

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.

You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.

If you wanted to actually program this on a real FPGA, you’d have a little work to do. The memory and register initialization is done in a way that works fine for simulation, but wouldn’t work on a real FPGA. Anyway, let’s get started!

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Learn by Fixing: Another Verilog CPU

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. However, what was worse is one of the modules needed to get it to work was missing! You might argue it was an exercise left to the reader, but it probably should have been pointed out that way.

At first, I was ready to delete the bookmark and move on. Then I decided that the process of fixing this design and doing a little analysis on it might actually be more instructive than just studying a fully working design. So I decided to share my fix with you and look inside the architecture a bit more. On top of that, I’ll show you how to get the thing to run in an online simulator so you can experiment with no software installation. Of course, if you are comfortable with a Verilog toolchain (like the ones from Xilinx or Altera, or even free ones like Icarus or CVer) you should have no problem making that work, either. This time I’ll focus on how the CPU works and next time I’ll show you how to simulate it with some free tools. Continue reading “Learn by Fixing: Another Verilog CPU”