Video FPGA with No External A/D

You have an old PC with a nonstandard RGB video out and you need to bring it to a modern PAL TV set. That’s the problem [svofski] had, so he decided to use an Altera-based DE1 board to do the conversion. Normally, you’d expect reading an RGB video signal would take an analog to digital converter, which is not typically present on an FPGA. Instead of adding an external device, [svofski] used a trick to hijack the FPGA’s LVDS receivers and use them as comparators.

The scheme does take a few discrete components to level shift the input signal and to provide an RC integrator. The integrator is used as a digital to analog converter, allowing the FPGA to compare the incoming signal with an output voltage. Once the analog signal is digitized, it is relatively straightforward to convert it to any format you want. Going back to the analog domain is as simple as a pulse width or pulse density modulation scheme and an RC filter (or you could use a simple R2R DAC).

The result is a very low parts count project that gets the job done. Of course, this is a complete hack of the LVDS I/O in the FPGA. If you want to hear more about the real use of LVDS, see the video below.

23 thoughts on “Video FPGA with No External A/D

  1. I was intending to use some op-amps and write up some VHDL to use the single op-amp and a capacitor with single bit modulation to convert an analog signal to a binary stream. From there it would be easy to bring it back to meaningful info with FPGA as it’s already binary.

    This helps heaps, thanks [Al Williams] – now I don’t need the op-amps.

    Since you mentioned Pulse Width Modulation and Pulse Density Modulation, I thought I would mention Bit Angle Modulation. BAM has it’s place in micro-controllers when you need to bit bang several (PWM like) analog outputs. It has predictable interrupt event timings. I suspect BAM may also be useful for FPGA.

    Bit Angle Modulation vs PWM –

    Mirrored BAM –

      1. BAM is indeed not as straightforward to implement as PWM. It requires more ressources than PWM for the same amount of channels.

        PWM requires one constant comparator (==0), n flip-flops and a subtractor with a constant (1).
        BAM would require one constant comparator, n flip flops, one n bit mux, and a subtractor.
        PDM only requires one n bits counter.

        The only advantage I see for BAM is more transitions and therefore more high-frequency content. It means easier to filter than PWM, not as good as PDM though.

        1. the system shown is a first order delta sigma converter, the dac version can be done with a single carry in-out adder

          I believe Xilinx actually have a patent on using a LVDS reciever as the comparator for an ADC in an FPGA

          1. The papers that I used used to be on Lattice website, but later they were either removed or maybe moved somewhere else. Not sure if because of IP disputes or simply because of some mindless website rework.

          2. @fonz

            Only Fig 3 on the third page shows any FPGA. Also I see this as a ‘patent application’ has it even been accepted?

            What I wanted to do is very similar to Fig 3 in that I wanted to go directly to single bit and expand the bit width from there. Fig 3 has a problem where it would have two stages of quantising error if used this way and as it’s drawn it simply would not work.

        2. BAM may have other useful points.

          In PWM the output contains two primary frequencies (and their harmonics) and those frequencies vary in steps across a very broad range.

          With BAM you have one primary frequency and 7 (or n bits -1) primary harmonics and then the secondary harmonics after that so you may be able to use it where you have a sensitivity to particular frequencies by keeping well away from the sensitivities.

        3. Why a substractor? Sorry I’m pretty New to FPGAs, but i would usw a counter (with overflow instead of comparator), n registers w/ the target duty cycle and n*bits xors and inverters ORed together. Then the outputs would be high if one or more of the bits is active. Am I missing something?

    1. @Felipe, your project is fantastic! You went much farther than I did. And the writeup is excellent. Thanks for sharing.

      If I understand correctly you’ve implemented a successive approximation ADC using LVDS inputs, is that right? I did not fully understand the part about a thermometer, is that a metaphor? Anyway, the results look beautiful.

      1. Yes I need 8 tests for a 3-bit accuracy. You go from 0 to 7 on your 3-pins output and test each voltage and concatenate a value. This gives you a 8-bit table that must be interpreted like the thermometer. It’s not a true byte. In case you have a value with holes like : 0001011 this is an error caused by a fluctuation when testing the 2 bit. It should be interpreted as 00001111, or Half-voltage. I make an error correction in the code.

        1. I see, that wasn’t entirely obvious. This indeed can be imagined as a thermometer.

          CoCo must have very stable video outputs if 3 bits is enough resolution. In my case I really needed more because the signal in Vector-06c tends to swing wildly during the sync pulses, due to insufficient value of the output capacitor (also thanks to lack of equalizing pulses and thanks to aging of electrolyte).

          This is a typical end of frame, you can see what I’m talking about:

      2. The thermometer seems to be the bit stream from the LVDS comparator that needs further processing because there is no *sample* and hold. It is comparing a live and moving analog input.

  2. Wonder if there would be a way to use some tiny cheap GTL (Gunning Transceiver Logic) chips (e.g., FIN1002)? If so, it would be line powered (maybe). Anyway, it took me longer to write this than I’ve thought about it – so probably not…

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