If you read my first post about a simple CPLD do-it-yourself project you may remember that I seriously wiffed when I made the footprint 1” wide, which was a bit too wide for common solderless breadboards. Since then I started over, having fixed the width problem, and ended up with a module that looks decidedly… cuter.
To back up a little bit, a Complex Programmable Logic Device (CPLD) is a cool piece of hardware to have in your repertoire and it can be used to learn logic or a high level design language or replace obsolete functions or chips. But a CPLD needs a little bit of support infrastructure to become usable, and that’s what I’ll be walking you through here. So if you’re interested in learning CPLDs, or just designing boards for them, read on!
The design itself tries to utilize through-hole parts and a socket for the CPLD so that you could more easily build it yourself without a lot of surface mount soldering. With that said, the oscillator is a surface mount device (SMD) just due to the cost and size of its through-hole counterpart.
I also added a USB Mini connector to make it easier to power the assembly, like when making a video for Hackaday. I am only partially happy with the USB connector approach as it is useful only for the 5V version and dangerous if the 3.3V CPLD is used. I also added a two-pin connector for power at the last minute but really would like to have added a diode to protect against reverse polarity.
In addition, an external clock source may easily be applied via a connector thanks to a suggestion/comment from the last post.
- Simple CPLD R2 Schematic
- Simple CPLD R2 PCB Layout
- Simple CPLD R2 BOM
- Gerber Files Simple CPLD R2
- Gerber Files Simple CPLD R2 (OSH Park Compatible)
- Simple CPLD R2 Proteus CAD Project
- CPLD R2 Quartus Design Files
- Altera Quartus 9.1 Web Edition (Free)
The CPLD: A surface mount part that fits a through-hole socket
This part known as either the EPM7032 or EPM7064, comes in a 44 pin plastic leaded chip carrier (PLCC) which is sometimes called J lead due to the J shape of the pin leads. This package can be inserted in a through-hole socket or directly soldered to the PCB.
These parts tend to cost $8-$9USD from the standard catalog sources. I have a batch coming from overseas at a much cheaper price, if anyone is looking to build several units where a cheaper source pays off then message me.
The original on-board oscillator is a 25 MHz device, mostly because “fast” is usually good. In real life I think a 4 MHz or a special frequency such as 14.318 MHz (NTSC x 4) or 1.8432 MHz (UART) may be more useful for slower logic as the clock does not need to be divided down as much. With that said, it’s easy to use a different TCO or to apply an external clock to the pins provided.
Programming the CPLD
The 10 pin connector and a handful of resistors comprise the programming circuit, this footprint is often called the JTAG connector.
To program a standalone CPLD like this one, a dedicated programmer is needed. An approved “Altera USB Blaster” costs $50 and is available from places like Digikey. I have several clones that I got off of eBay including one that is a clone that supports Altera, Xilinx and Lattice all in one.
Down the road I hope to do a programmer clone project, the parts are sitting on the table next to me.
The PCB is a simple two-sided design, however assembly requires first installing the 40 position “machined” pins from the bottom, clipping the leads short, and then installing the socket from the top.
The 3D View
Lots of I/O
The first thing that jumps out when using one of these CPLD modules is the large number of Input/Output (I/O) lines available from the 40 pin package, 35 I/O lines to be exact. There could have been more except I like to make sure there are several ground pins. As the name implies, I/O lines can be programmed to be inputs, outputs or bi-directional and can also tristate and simulate open-collector outputs.
The other feature of a module like this is the speed; it switches in nanoseconds instead of the microsecond speeds found in many microcontrollers.
The CPLD Design
The entire design contains all of the files needed to quickly utilize the Simple CPLD board including the pin and device assignments. To use this design, download Quartus Web 9.1 and install. Download the design, unzip and open the project Simple-CPLD-Demo.qpf. Click on the Files Tab under Project Navigator and you should see the three important files:
- top.bdf – The top of the project as a graphical block diagram file (bdf)
- block1.v – The Verilog file for the symbol named
block1o. the bdf
- waveform1.vwf – The waveform that drives the simulation
The lpm_counter0.qip file was installed automatically by the compiler.
The Schematic (bdf)
Clicking on top.bdf brings up the top sheet. I still make the top sheet a graphical sheet but you could forego this and use Verilog or VHDL. (I used to use AHDL 25 years ago)
On the schematic we see a functional block aptly named
block1 that represents the Verilog file underneath it. Shown are also are the pins representing the chip pins themselves.
Click on Assignments, Assignment Editor to see the pin name to pin number assignments. Again I name the pin in a way that makes it easy to assign the pin number, I.E. IO11 is Pin 11.
The Verilog File
On the top.bdf file, double-click on the symbol
block1 and the underlying Verilog file is opened in a text editor. The built-in text editor is pretty reasonable, however a lot of use like to assign an external editor, in my case I use Notepad++ with the Verilog colorizer tweaked to my own preference for colors.
Here all of the assignments have been made to match the block to match the project to match the PCB.
Click on the purple “play” button to compile the design.
Click on the file waveform1.vwf and the input to the simulation will be opened in the waveform editor. (I have mine preset to use pretty colors). The only input to the demo is the clock. To change the clock’s timing as an example, right click on the clock waveform and select Value, Clock, and change the clocks frequency and duty cycle.
Click on the Simulation Icon and the resulting waveform should open up with the results of the simulation of the design, a couple of counters in this case.
Programming the CPLD
Plug your programmer into the 10 pin JTAG connector noting the Pin 1 locator dot on the PCB which should line up with Pin 1 on your programmer plug or the Pin 1 stripe on the cable itself.
Once satisfied with the output, or if you’re the adventurous type and want to jump straight to trying the design on actual hardware, simply click on the Programmer Icon. You should see your programmer listed (USB-Blaster here) and the file Simple-CPLD-Demo.pof and the device you selected earlier. If it isn’t present, click Add File and select it. Select the checkboxes for Program, Configure, and Verify and click Start.
If everything works correctly you should see a message about the success in the ever-present message box and in my case my LEDs started to blink.
I wanted to demonstrate a beginning-to-end experience for the beginner. Starting with this Simple CPLD module you can be up and running in a few minutes. You can also start learning/editing Verilog using the file provided or replace or add graphical components to the top sheet if you would rather design using a schematic.
The CPLD is electrically erasable meaning you can reprogram it over and over and in between it will retain the configuration unlike many FPGAs that have to be programmed every power cycle, making it ideal for small and medium size application. Build along and have fun!